Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

--- Title:IndustrialIO_top.vhd

--- Description: 

---

---     o  0

---     | /       Copyright (c) 2010

---    (CL)---o   Critical Link, LLC

---      \

---       O

---

--- Company: Critical Link, LLC.

--- Date: 03/7/2010

--- Version: 1.00

---

--- Revision History

---   1.00 - Initial revision

---   1.10 - REVISION TO AGREE WITH CUSTOM BOARD ANALOG1

library WORK;

library IEEE;

library UNISIM;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use UNISIM.VCOMPONENTS.ALL;

use WORK.MityDSP_L138_pkg.ALL;

entity IndustrialIO_top is

   generic ( BOARD_REV     : string := "C"; -- "A", "B", or "C"

             DECODE_BITS   : integer range 1 to 9 := 9;

             CAMERA_CONFIG : string := "NONE"; -- "RAW" - route camera I/O hack to RAW Video input interface 

             DISP_CONFIG   : string := "LCD"; -- "LCD", "DVI" or "NONE"

             LCD_TYPE      : string := "SHARP"  -- "SHARP" or "NEC"

   );

   port (

      i_ema_clk	      : in std_logic; -- 100 MHz EMIF clock

      -- DSP EMIFA BUS Interface

      i_ema_cs0_n   : in std_logic; -- RESERVED for SDRAM Controller

      i_ema_cs2_n   : in std_logic; -- ARM core CE space

      i_ema_cs3_n   : in std_logic; -- NAND FLASH space, not used

      i_ema_cs4_n   : in std_logic; -- DSP core CE space

      i_ema_cs5_n   : in std_logic; -- Reserved core space, not used

      i_ema_oe_n    : in std_logic;

      i_ema_we_n    : in std_logic;

      io_ema_wait_n : inout std_logic_vector(1 downto 0);

      io_ema_d      : inout std_logic_vector(15 downto 0);

      i_ema_a       : in std_logic_vector(13 downto 0);

      i_ema_ba      : in std_logic_vector(1 downto 0);

      i_ema_wen_dqm : in std_logic_vector(1 downto 0); 

      i_ema_cas     : in std_logic; -- reserved for SDRAM controller, not used

      i_ema_ras     : in std_logic; -- reserved for SDRAM controller, not used

      i_ema_sdcke   : in std_logic; -- reserved for SDRAM controller, not used

      i_ema_rnw     : in std_logic; -- reserved for SDRAM controller, not used

--      -- DSP LCD Interface

--      i_lcd_d       : in std_logic_vector(15 downto 0);

--      i_lcd_hsync   : in std_logic;

--      i_lcd_vsync   : in std_logic;

--      i_lcd_mclk    : in std_logic;

--      i_lcd_pclk    : in std_logic;

--      i_lcd_enb     : in std_logic;

--      -- LCD Differential Serializer Interface

--      o_disp_a0_p   : out std_logic;

--      o_disp_a0_n   : out std_logic;

--      o_disp_a1_p   : out std_logic;

--      o_disp_a1_n   : out std_logic;

--      o_disp_a2_p   : out std_logic;

--      o_disp_a2_n   : out std_logic;

--      o_disp_a3_p   : out std_logic;

--      o_disp_a3_n   : out std_logic;

--      o_disp_clkin_p: out std_logic;

--      o_disp_clkin_n: out std_logic;

--      -- Touch screen interface

--      o_ts_cs_n      : out std_logic;

--      o_ts_clk       : out std_logic;

--      o_ts_din       : out std_logic;

--      i_ts_dout      : in  std_logic;

--      i_ts_busy      : in  std_logic;

--      io_ts_PenIRQ_n : inout  std_logic;

--      o_disp_cs_n    : out std_logic;

--      

--      -- DVI controller interface

--      io_sda         : inout std_logic;

--      o_scl          : out std_logic;

--      

--      o_dvi_data     : out std_logic_vector(15 downto 0);

--      o_dvi_clk      : out std_logic;

--      o_dvi_hsync    : out std_logic;

--      o_dvi_vsync    : out std_logic;

--      o_dvi_de       : out std_logic;

      -- DSP IRQ lines

      o_nmi_n       : out std_logic;

      o_int         : out std_logic_vector(1 downto 0);

--      -- CAMERA input interface (for camera demo)

--      i_cam_data    : in std_logic_vector(9 downto 0);

--      i_cam_lv      : in std_logic;

--      i_cam_fv      : in std_logic;

--      i_cam_pclk    : in std_logic;

--      

--      -- Raw Video Interface (for camera demo)

--      o_vp_clkin     : out std_logic_vector(1 downto 0);

--      o_vp_hsync      : out std_logic;

--      o_vp_vsync      : out std_logic;

--		o_vp_field      : out std_logic;

--      o_vp_din        : out std_logic_vector(12 downto 0);

--		

--		-- camera demo misc signals

--		o_pwm           : out std_logic_vector(1 downto 0);

--		o_diode         : out std_logic_vector(1 downto 0);

		-- dac cal&offset control signals 

		o_dac_cal_ctrl: out std_logic_vector(5 downto 0);

		-- ext gpio control signals

		o_ext_gpio: out std_logic_vector(1 downto 0);

		-- ia write enable signals

		o_ia_wr: out std_logic_vector(3 downto 0);

		-- channel configuration control signals

		o_chann_config: out std_logic_vector(2 downto 0);

		-- FSPI_1 signals

		o_fspi1_mosi: out std_logic;

		i_fspi1_miso: in std_logic;

		o_fspi1_clk: out std_logic;

		o_fspi1_cs: out std_logic_vector (7 downto 0);

		-- FSPI_2 signals

		o_fspi2_mosi: out std_logic;

		i_fspi2_miso: in std_logic;

		o_fspi2_clk: out std_logic;

		o_fspi2_cs: out std_logic_vector (7 downto 0);

--		-- FIFO1 signals		

--		o_fifo1_full: out std_logic;

--		o_fifo1_mid: out std_logic;

--		o_fifo1_low: out std_logic;

--		o_fifo1_empty: out std_logic;

--		

--		-- FIFO2 signals		

--		o_fifo2_full: out std_logic;

--		o_fifo2_mid: out std_logic;

--		o_fifo2_low: out std_logic;

--		o_fifo2_empty: out std_logic;

		-- sampling clock manager

		i_from_out_conv: in std_logic;

		o_to_in_conv: out std_logic

  );

end IndustrialIO_top;

--------------------------------------------------------------------------

-- ARCHITECTURE

--------------------------------------------------------------------------

architecture rtl of IndustrialIO_top is

constant FPGA_APPLICATION_ID: std_logic_vector(7 downto 0) := CONV_STD_LOGIC_VECTOR( 00, 8);

constant FPGA_VERSION_MAJOR:  std_logic_vector(3 downto 0) := CONV_STD_LOGIC_VECTOR( 01, 4);

constant FPGA_VERSION_MINOR:  std_logic_vector(3 downto 0) := CONV_STD_LOGIC_VECTOR( 00, 4);

constant FPGA_YEAR:           std_logic_vector(4 downto 0) := CONV_STD_LOGIC_VECTOR( 10, 5);

constant FPGA_MONTH:          std_logic_vector(3 downto 0) := CONV_STD_LOGIC_VECTOR( 04, 4);

constant FPGA_DAY:            std_logic_vector(4 downto 0) := CONV_STD_LOGIC_VECTOR( 20, 5);

constant CORE_BASE_MODULE: integer := 0;

constant CORE_DAC_CAL_CTRL_MODULE: integer:= 1;

constant CORE_EXT_GPIO_MODULE: integer:= 2;

constant CORE_IA_WR_MODULE: integer:= 3;

constant CORE_CHANN_CONFIG_MODULE:integer:= 4;

constant CORE_SPI1_MODULE: integer:= 5;

constant CORE_SPI2_MODULE: integer:= 6;

constant CORE_DAC_CAL_CTRL_IRQ_LEVEL : integer := 0;

constant CORE_DAC_CAL_CTRL_IRQ_VECTOR: integer := 0;

constant CORE_EXT_GPIO_IRQ_LEVEL: integer := 0;

constant CORE_EXT_GPIO_IRQ_VECTOR: integer := 1;

constant CORE_IA_WR_IRQ_LEVEL: integer := 0;

constant CORE_IA_WR_IRQ_VECTOR: integer := 2;

constant CORE_CHANN_CONFIG_IRQ_LEVEL: integer:= 0;

constant CORE_CHANN_CONFIG_IRQ_VECTOR: integer:= 3;

constant CORE_SPI1_IRQ_LEVEL: integer :=1;

constant CORE_SPI1_IRQ_VECTOR: integer :=1;

constant CORE_SPI2_IRQ_LEVEL: integer :=1;

constant CORE_SPI2_IRQ_VECTOR: integer :=2;

--constant CORE_TS_MODULE     : integer := 1;

--constant CORE_I2C_MODULE    : integer := 2;

--constant CORE_LCD_MODULE    : integer := 3;

--constant CORE_DVI_MODULE    : integer := 4;

--constant CORE_GPIO_MODULE   : integer := 5;

--constant CORE_PWM_MODULE    : integer := 6;

--constant CORE_TS_IRQ_LEVEL  : integer := 0;

--constant CORE_TS_IRQ_VECTOR : integer := 0;

--constant CORE_I2C_IRQ_LEVEL  : integer := 0;

--constant CORE_I2C_IRQ_VECTOR : integer := 1;

--constant CORE_LCD_IRQ_LEVEL  : integer := 0;

--constant CORE_LCD_IRQ_VECTOR : integer := 2;

--constant CORE_DVI_IRQ_LEVEL  : integer := 0;

--constant CORE_DVI_IRQ_VECTOR : integer := 3;

--constant CORE_GPIO_IRQ_LEVEL : integer := 1;

--constant CORE_GPIO_IRQ_VECTOR : integer := 0;

--constant CORE_PWM_IRQ_LEVEL     : integer := 1;

--constant CORE_PWM_IRQ_VECTOR    : integer := 1;

-- FIFO DPRAM 64x32 BUFFER FOR SPI

-- THIS COMPONENT HAS BEEN PROGRAMMED TO HAVE 4 THRESHOLD

-- USING CORE GENERATOR fifo_dpram64x32.xco

-- FIFO BUFFER DOES NOT HOOK TO EMIF, ONLY EMIF VIA SPI CORE

-- FULL: 64 BLOCKS

-- MID : 48 BLOCKS

-- LOW : 16 BLOCKS

-- EMPTY : 0 BLOCKS

component fifo_dpram64x32

	port (

	clk: in std_logic;

	rst: in std_logic;

	din: in std_logic_vector(31 downto 0);

	wr_en: in std_logic;

	rd_en: in std_logic;

	dout: out std_logic_vector(31 downto 0);

	full: out std_logic;

	empty: out std_logic;

	data_count: out std_logic_vector(5 downto 0);

	prog_full: out std_logic;

	prog_empty: out std_logic);

end component;

-- clock/reset related signals

signal clk25mhz: std_logic;

signal ema_clk: std_logic;

signal dcm_lock: std_logic;

signal dcm_reset: std_logic;

signal dcm_status: std_logic_vector(2 downto 0);

signal wd_rst: std_logic;

-- EMIFA interface signals

signal ema_d : std_logic_vector(15 downto 0);

signal ema_wait_n : std_logic_vector(1 downto 0) := "11";

signal t_ema_wait : std_logic;

signal t_ema_d : std_logic;

signal be_r : std_logic_vector(1 downto 0);

signal addr_r : std_logic_vector(5 downto 0);

signal arm_cs5_r : std_logic_vector((2**DECODE_BITS)-1 downto 0);

signal dsp_cs4_r : std_logic_vector((2**DECODE_BITS)-1 downto 0);

signal edi_r : std_logic_vector(15 downto 0);

signal edo_arm : bus16_vector((2**DECODE_BITS)-1 downto 0);

signal edo_dsp : bus16_vector((2**DECODE_BITS)-1 downto 0);

signal rd_r : std_logic;

signal wr_r : std_logic;

signal irq_map  : bus16_vector(1 downto 0) := (others=>(others=>'0')); 

-- Hook up signals for SPI cores (SPI to BUFFER FIFO) SPI CORE 1

signal mosi1_din : std_logic_VECTOR(31 downto 0);

signal mosi1_wr_en : std_logic;

signal mosi1_rd_en : std_logic;

signal mosi1_dout : std_logic_VECTOR(31 downto 0);

signal mosi1_full : std_logic;

signal mosi1_empty : std_logic;

signal mosi1_wr_data_count : std_logic_VECTOR(11 downto 0) := (others=>'0');

signal spi1_fifo_rst : std_logic := '0';

signal miso1_wr_clk : std_logic;

signal miso1_rd_clk : std_logic;

signal miso1_din : std_logic_VECTOR(31 downto 0);

signal miso1_wr_en : std_logic;

signal miso1_rd_en : std_logic;

signal miso1_dout : std_logic_VECTOR(31 downto 0);

signal miso1_empty : std_logic;

signal miso1_rd_data_count : std_logic_VECTOR(11 downto 0) := (others=>'0');

signal spi1_cs : std_logic_vector(7 downto 0) := (others=>'1');

signal spi1_clk, spi1_mosi : std_logic := '0';

-- Hook up signals for SPI cores (SPI to BUFFER FIFO) SPI CORE 2

signal mosi2_din : std_logic_VECTOR(31 downto 0);

signal mosi2_wr_en : std_logic;

signal mosi2_rd_en : std_logic;

signal mosi2_dout : std_logic_VECTOR(31 downto 0);

signal mosi2_full : std_logic;

signal mosi2_empty : std_logic;

signal mosi2_wr_data_count : std_logic_VECTOR(11 downto 0) := (others=>'0');

signal spi2_fifo_rst : std_logic := '0';

signal miso2_wr_clk : std_logic;

signal miso2_rd_clk : std_logic;

signal miso2_din : std_logic_VECTOR(31 downto 0);

signal miso2_wr_en : std_logic;

signal miso2_rd_en : std_logic;

signal miso2_dout : std_logic_VECTOR(31 downto 0);

signal miso2_empty : std_logic;

signal miso2_rd_data_count : std_logic_VECTOR(11 downto 0) := (others=>'0');

signal spi2_cs : std_logic_vector(7 downto 0) := (others=>'1');

signal spi2_clk, spi2_mosi : std_logic := '0';

---- LCD Signals

--signal serdes_clk : std_logic;

--signal serdes_ctl : std_logic;

--signal serdes_b : std_logic;

--signal serdes_g : std_logic;

--signal serdes_r : std_logic; 

--signal serdes_debug : std_logic_vector(7 downto 0);

--signal lcd_pclk : std_logic;

--signal ts_PenIRQ_n : std_logic;

--signal t_ts_PenIRQ_n : std_logic;

--signal lcd_hrev : std_logic;

--signal lcd_dim_pwm : std_logic;

--signal lcd_pwr : std_logic;

--signal lcd_backlit : std_logic;

--signal lcd_vrev : std_logic;

--signal lcd_en : std_logic;

--

---- DVI signals

--signal sda, t_sda : std_logic;

--signal dvi_data_c0 : std_logic_vector(11 downto 0);

--signal dvi_data_c1 : std_logic_vector(11 downto 0);

--signal dvi_clk : std_logic;

--

---- camera interface

--signal cam_lv : std_logic := '0';

--signal cam_fv : std_logic := '0';

--signal cam_data : std_logic_vector(9 downto 0) := (others=>'0');

--signal cam_pclk : std_logic := '0';

--signal t_cam_sdat : std_logic := '1';

--signal cam_sdat : std_logic := '0';

--signal h_cnt : std_logic_vector(9 downto 0) := (others=>'0');

--signal l_cnt : std_logic_vector(8 downto 0) := (others=>'0');

--signal ema_clk_div : std_logic_vector(1 downto 0) := (others=>'0');

--signal temp_clk : std_logic;

begin -- architecture: rtl

--------------------------------------------------------------------------

-- System DCM Instantiation

--------------------------------------------------------------------------

--------------------------------------------------------------------------

-- Clock Buffer Instantiation

--------------------------------------------------------------------------

-- TODO -- DCM???

emaclkbuf : bufg port map (O => ema_clk, I => i_ema_clk);

--pclkbuf : bufg port map (O => lcd_pclk, I=> i_lcd_pclk);

-- ema_clk <= i_ema_clk;

o_to_in_conv <= i_from_out_conv;

------------------------------------------------------------------------------

-- EMIF Interface Module: 

------------------------------------------------------------------------------

emififace : EMIFA_iface

    generic map ( 

        DECODE_BITS       => DECODE_BITS, 

        CONFIG            => "MityDSP_L138" 

    )

    port map ( ema_clk   => ema_clk, 

           -- EMIFA signals

           i_ema_cs0_n   => i_ema_cs0_n, 

           i_ema_cs2_n   => i_ema_cs2_n, 

           i_ema_cs3_n   => i_ema_cs3_n, 

           i_ema_cs4_n   => i_ema_cs4_n, 

           i_ema_cs5_n   => i_ema_cs5_n, 

           i_ema_oe_n    => i_ema_oe_n, 

           i_ema_we_n    => i_ema_we_n, 

           o_ema_wait_n  => ema_wait_n, 

           t_ema_wait    => t_ema_wait, 

           i_ema_d       => io_ema_d, 

           o_ema_d       => ema_d, 

           t_ema_d       => t_ema_d, 

           i_ema_a       => i_ema_a, 

           i_ema_ba      => i_ema_ba, 

           i_ema_wen_dqm => i_ema_wen_dqm,  

           i_ema_cas     => i_ema_cas,  

           i_ema_ras     => i_ema_ras,  

           i_ema_sdcke   => i_ema_sdcke,  

           i_ema_rnw     => i_ema_rnw,  

           -- FPGA fabric signals

           o_core_be      => be_r,  

           o_core_addr    => addr_r,  

           o_core_cs5     => arm_cs5_r,  

           o_core_cs4     => dsp_cs4_r,  

           o_core_edi     => edi_r,  

           i_core_edo5    => edo_arm,  

           i_core_edo4    => edo_dsp,  

           o_core_rd      => rd_r,  

           o_core_wr      => wr_r  

    );

------------------------------------------------------------------------------

-- Base Module

------------------------------------------------------------------------------

bm : base_module

   generic map (

      CONFIG => "MityDSP_L138"

      )

   port map (

      ema_clk         => ema_clk, 

      i_cs            => arm_cs5_r(CORE_BASE_MODULE),

      i_ID            => FPGA_APPLICATION_ID,

      i_version_major => FPGA_VERSION_MAJOR,

      i_version_minor => FPGA_VERSION_MINOR,

      i_year          => FPGA_YEAR,

      i_month         => FPGA_MONTH,

      i_day           => FPGA_DAY,

      i_ABus          => addr_r,

      i_DBus          => edi_r,

      o_DBus          => edo_arm(CORE_BASE_MODULE),

      i_wr_en         => wr_r,

      i_rd_en         => rd_r,

      i_be_r          => be_r,

      o_dcm_reset  => open,

      i_dcm_status => dcm_status,

      i_dcm_lock   => dcm_lock,

      i_irq_map    => irq_map,

      o_irq_output => o_int                  

      );

-------------------------------------------------------------------------

-- DAC CALIBRATION CONTROL GPIO CORE

-------------------------------------------------------------------------

dac_cal_ctrl_inst: gpio 

generic map(

NUM_BANKS => 1,

NUM_IO_PER_BANK =>6

)

port map(

      clk             => ema_clk,

      i_ABus          => addr_r,

      i_DBus          => edi_r,

      o_DBus          => edo_arm(CORE_DAC_CAL_CTRL_MODULE),

      i_wr_en         => wr_r,

      i_rd_en         => rd_r,

      i_cs            => arm_cs5_r(CORE_DAC_CAL_CTRL_MODULE),

      o_irq           => irq_map(CORE_DAC_CAL_CTRL_IRQ_LEVEL)(CORE_DAC_CAL_CTRL_IRQ_VECTOR),

      i_ilevel        => conv_std_logic_vector(CORE_DAC_CAL_CTRL_IRQ_LEVEL, 2),     

      i_ivector       => conv_std_logic_vector(CORE_DAC_CAL_CTRL_IRQ_VECTOR, 4),   

      i_io            => "000000",

      t_io            => open,

      o_io            => o_dac_cal_ctrl,

      i_initdir       => "111111",

      i_initoutval    => "111111"	

);

--------------------------------------------------------------------------

--EXTERNAL GPIO CONTROL CORE

--------------------------------------------------------------------------

ext_gpio_inst: gpio 

generic map(

NUM_BANKS => 1,

NUM_IO_PER_BANK =>2

)

port map(

      clk             => ema_clk,

      i_ABus          => addr_r,

      i_DBus          => edi_r,

      o_DBus          => edo_arm(CORE_EXT_GPIO_MODULE),

      i_wr_en         => wr_r,

      i_rd_en         => rd_r,

      i_cs            => arm_cs5_r(CORE_EXT_GPIO_MODULE),

      o_irq           => irq_map(CORE_EXT_GPIO_IRQ_LEVEL)(CORE_EXT_GPIO_IRQ_VECTOR),

      i_ilevel        => conv_std_logic_vector(CORE_EXT_GPIO_IRQ_LEVEL, 2),     

      i_ivector       => conv_std_logic_vector(CORE_EXT_GPIO_IRQ_VECTOR, 4),   

      i_io            => "00",

      t_io            => open,

      o_io            => o_ext_gpio,

      i_initdir       => "11",

      i_initoutval    => "11"	

);

-----------------------------------------------------------------------------

--INSTRUMENTATION AMPLIFIER ENABLE CONTROL

-----------------------------------------------------------------------------

ia_wr_inst: gpio 

generic map(

NUM_BANKS => 1,

NUM_IO_PER_BANK =>4

)

port map(

      clk             => ema_clk,

      i_ABus          => addr_r,

      i_DBus          => edi_r,

      o_DBus          => edo_arm(CORE_IA_WR_MODULE),

      i_wr_en         => wr_r,

      i_rd_en         => rd_r,

      i_cs            => arm_cs5_r(CORE_IA_WR_MODULE),

      o_irq           => irq_map(CORE_IA_WR_IRQ_LEVEL)(CORE_IA_WR_IRQ_VECTOR),

      i_ilevel        => conv_std_logic_vector(CORE_IA_WR_IRQ_LEVEL, 2),     

      i_ivector       => conv_std_logic_vector(CORE_IA_WR_IRQ_VECTOR, 4),   

      i_io            => "0000",

      t_io            => open,

      o_io            => o_ia_wr,

      i_initdir       => "1111",

      i_initoutval    => "1111"	

);

--------------------------------------------------------------------------------

--CHANNEL CONFIGURATION CONTROL GPIO CORE

--------------------------------------------------------------------------------

chann_config_inst: gpio 

generic map(

NUM_BANKS => 1,

NUM_IO_PER_BANK =>3

)

port map(

      clk             => ema_clk,

      i_ABus          => addr_r,

      i_DBus          => edi_r,

      o_DBus          => edo_arm(CORE_CHANN_CONFIG_MODULE),

      i_wr_en         => wr_r,

      i_rd_en         => rd_r,

      i_cs            => arm_cs5_r(CORE_CHANN_CONFIG_MODULE),

      o_irq           => irq_map(CORE_CHANN_CONFIG_IRQ_LEVEL)(CORE_CHANN_CONFIG_IRQ_VECTOR),

      i_ilevel        => conv_std_logic_vector(CORE_CHANN_CONFIG_IRQ_LEVEL, 2),     

      i_ivector       => conv_std_logic_vector(CORE_CHANN_CONFIG_IRQ_VECTOR, 4),   

      i_io            => "000",

      t_io            => open,

      o_io            => o_chann_config,

      i_initdir       => "111",

      i_initoutval    => "111"	

);

----------------------------------------------------------------

-- SPI CORE N.1

----------------------------------------------------------------

spi1_core : spi

Port Map ( 

emif_clk => ema_clk, 

i_ABus => addr_r,

i_DBus => edi_r,

o_DBus => edo_dsp(CORE_SPI1_MODULE),

i_wr_en => wr_r,

i_rd_en => rd_r,

i_cs => dsp_cs4_r(CORE_SPI1_MODULE),

o_irq => irq_map(CORE_SPI1_IRQ_LEVEL)(CORE_SPI1_IRQ_VECTOR),

i_ilevel => CONV_STD_LOGIC_VECTOR(CORE_SPI1_IRQ_LEVEL,2),

i_ivector => CONV_STD_LOGIC_VECTOR(CORE_SPI1_IRQ_VECTOR,4),

-- SPI interface signals 

o_sclk => o_fspi1_clk,

o_cs_n => o_fspi1_cs,

o_mosi => o_fspi1_mosi,

i_miso => i_fspi1_miso,

-- In/Out FIFO interfaces (NO FIRST WORD FALLTHROUGH)

-- Synchronous on emif_clock

i_fifo_depth => "010",

o_mosi_fifo_wr => mosi1_wr_en,

o_mosi_fifo_rd => mosi1_rd_en,

o_mosi_fifo_in => mosi1_din, -- fifo data input

i_mosi_fifo_out => mosi1_dout,

i_mosi_write_cnt => mosi1_wr_data_count,

i_mosi_empty => mosi1_empty,

o_miso_fifo_wr => miso1_wr_en,

o_miso_fifo_rd => miso1_rd_en,

o_miso_fifo_in => miso1_din,

i_miso_fifo_out => miso1_dout,

i_miso_read_cnt => miso1_rd_data_count,

i_miso_empty => miso1_empty,

o_fifo_rst => spi1_fifo_rst

);

--o_cs_n <= o_fspi1_cs(0);

--o_sdi <= spi_mosi;

mosi1_fifo : fifo_dpram64x32

port map (

clk => ema_clk,

rst => spi1_fifo_rst,

din => mosi1_din,

wr_en => mosi1_wr_en,

rd_en => mosi1_rd_en,

dout => mosi1_dout,

full => open,

empty => mosi1_empty,

data_count => mosi1_wr_data_count(5 downto 0),

prog_full => open,

prog_empty => open

); 

miso1_fifo : fifo_dpram64x32

port map (

clk => ema_clk,

rst => spi1_fifo_rst,

din => miso1_din,

wr_en => miso1_wr_en,

rd_en => miso1_rd_en,

dout => miso1_dout,

full => open,

empty => miso1_empty,

data_count => miso1_rd_data_count(5 downto 0),

prog_full => open,

prog_empty => open

);

----------------------------------------------------------------

-- SPI CORE N.2

----------------------------------------------------------------

spi2_core : spi

Port Map ( 

emif_clk => ema_clk, 

i_ABus => addr_r,

i_DBus => edi_r,

o_DBus => edo_dsp(CORE_SPI2_MODULE),

i_wr_en => wr_r,

i_rd_en => rd_r,

i_cs => dsp_cs4_r(CORE_SPI2_MODULE),

o_irq => irq_map(CORE_SPI2_IRQ_LEVEL)(CORE_SPI2_IRQ_VECTOR),

i_ilevel => CONV_STD_LOGIC_VECTOR(CORE_SPI2_IRQ_LEVEL,2),

i_ivector => CONV_STD_LOGIC_VECTOR(CORE_SPI2_IRQ_VECTOR,4),

-- SPI interface signals 

o_sclk => o_fspi2_clk,

o_cs_n => o_fspi2_cs,

o_mosi => o_fspi2_mosi,

i_miso => i_fspi2_miso,

-- In/Out FIFO interfaces (NO FIRST WORD FALLTHROUGH)

-- Synchronous on emif_clock

i_fifo_depth => "010",

o_mosi_fifo_wr => mosi2_wr_en,

o_mosi_fifo_rd => mosi2_rd_en,

o_mosi_fifo_in => mosi2_din, -- fifo data input

i_mosi_fifo_out => mosi2_dout,

i_mosi_write_cnt => mosi2_wr_data_count,

i_mosi_empty => mosi2_empty,

o_miso_fifo_wr => miso2_wr_en,

o_miso_fifo_rd => miso2_rd_en,

o_miso_fifo_in => miso2_din,

i_miso_fifo_out => miso2_dout,

i_miso_read_cnt => miso2_rd_data_count,

i_miso_empty => miso2_empty,

o_fifo_rst => spi2_fifo_rst

);

--o_cs_n <= o_fspi2_cs(0);

--o_sdi <= spi_mosi;

mosi2_fifo : fifo_dpram64x32

port map (

clk => ema_clk,

rst => spi2_fifo_rst,

din => mosi2_din,

wr_en => mosi2_wr_en,

rd_en => mosi2_rd_en,

dout => mosi2_dout,

full => open,

empty => mosi2_empty,

data_count => mosi2_wr_data_count(5 downto 0),

prog_full => open,

prog_empty => open

); 

miso2_fifo : fifo_dpram64x32

port map (

clk => ema_clk,

rst => spi2_fifo_rst,

din => miso2_din,

wr_en => miso2_wr_en,

rd_en => miso2_rd_en,

dout => miso2_dout,

full => open,

empty => miso2_empty,

data_count => miso2_rd_data_count(5 downto 0),

prog_full => open,

prog_empty => open

);

--gen_disp : if DISP_CONFIG = "LCD" generate 

--begin

--

--lcd_control : lcd_ctlr

--   port map (

--      ema_clk        => ema_clk,

--      i_ABus         => addr_r,

--      i_DBus         => edi_r,

--      o_DBus         => edo_arm(CORE_LCD_MODULE),

--      i_wr_en        => wr_r,

--      i_rd_en        => rd_r,

--      i_cs           => arm_cs5_r(CORE_LCD_MODULE),

--      o_irq          => irq_map(CORE_LCD_IRQ_LEVEL)(CORE_LCD_IRQ_VECTOR),

--      i_ilevel       => conv_std_logic_vector(CORE_LCD_IRQ_LEVEL, 2),

--      i_ivector      => conv_std_logic_vector(CORE_LCD_IRQ_VECTOR, 4),

--      

--      o_lcd_hrev     => lcd_hrev,

--      o_lcd_dim_pwm  => lcd_dim_pwm,

--      o_lcd_pwr      => lcd_pwr,

--      o_lcd_backlit  => lcd_backlit,

--      o_lcd_vrev     => lcd_vrev,

--      o_lcd_en       => lcd_en

--                  

--      );

--

--gen_sharp : if LCD_TYPE = "SHARP" generate

--begin

--

--serdes :  lcd_serdes_cl000099

--   port map (

--      

--      -- LCD Controller interface (from OMAP-L138)

--      i_lcd_d       => i_lcd_d,

--      i_lcd_hsync   => i_lcd_hsync,

--      i_lcd_vsync   => i_lcd_vsync,

--      i_lcd_mclk    => i_lcd_mclk,

--      i_lcd_pclk    => lcd_pclk,

--      i_lcd_enb     => i_lcd_enb,

--      

--      -- LCD control signals (from core???)

--      i_lcd_hrev    => lcd_hrev,

--      i_lcd_dim_pwm => lcd_dim_pwm,

--      i_lcd_pwr     => lcd_pwr,

--      i_lcd_backlit => lcd_backlit,

--      i_lcd_vrev    => lcd_vrev,

--      i_lcd_en      => '1', -- TODO

--      

--      -- LvDS I/O pins for LCD and some control signals

--      o_serdes_clk  => serdes_clk,

--      o_serdes_ctl  => serdes_ctl,

--      o_serdes_b    => serdes_b,

--      o_serdes_g    => serdes_g,

--      o_serdes_r    => serdes_r,

--      

--      o_debug        => serdes_debug

--   );

--end generate gen_sharp;

--

--gen_nec : if LCD_TYPE = "NEC" generate

--begin

--

--serdes :  lcd_serdes_cl000119

--   port map (

--      

--      -- LCD Controller interface (from OMAP-L138)

--      i_lcd_d       => i_lcd_d,

--      i_lcd_hsync   => i_lcd_hsync,

--      i_lcd_vsync   => i_lcd_vsync,

--      i_lcd_mclk    => i_lcd_mclk,

--      i_lcd_pclk    => lcd_pclk,

--      i_lcd_enb     => i_lcd_enb,

--      

--      -- LCD control signals (from core)

--      i_lcd_backlit => lcd_backlit,

--      i_lcd_en      => '1', -- TODO

--      i_lcd_dim_pwm => lcd_dim_pwm,

--      i_lcd_pwr     => lcd_pwr,

--      i_lcd_reset   => '0',

--      

--      -- LvDS I/O pins for LCD and some control signals

--      o_serdes_clk  => serdes_clk,

--      o_serdes_ctl  => serdes_ctl,

--      o_serdes_b    => serdes_b,

--      o_serdes_g    => serdes_g,

--      o_serdes_r    => serdes_r

--   );

--   

--end generate gen_nec;

--

--tsctrl : ads7843

--   port map (

--      emif_clk       => ema_clk,

--      i_ABus         => addr_r,

--      i_DBus         => edi_r,

--      o_DBus         => edo_arm(CORE_TS_MODULE),

--      i_wr_en        => wr_r,

--      i_rd_en        => rd_r,

--      i_cs           => arm_cs5_r(CORE_TS_MODULE),

--      o_irq          => irq_map(CORE_TS_IRQ_LEVEL)(CORE_TS_IRQ_VECTOR),

--      i_ilevel       => conv_std_logic_vector(CORE_TS_IRQ_LEVEL, 2),

--      i_ivector      => conv_std_logic_vector(CORE_TS_IRQ_VECTOR, 4),

--

--      o_ts_cs_n      => o_ts_cs_n,

--      o_ts_clk       => o_ts_clk,

--      o_ts_din       => o_ts_din,

--      i_ts_dout      => i_ts_dout,

--      i_ts_busy      => i_ts_busy,

--      i_ts_PenIRQ_n  => io_ts_PenIRQ_n,

--      o_ts_PenIRQ_n  => ts_PenIRQ_n,

--      t_ts_PenIRQ_n  => t_ts_PenIRQ_n,

--      o_disp_cs_n    => o_disp_cs_n,

--      o_gpio_out     => open

--   );

--

--io_ts_PenIRQ_n <= 'Z' when t_ts_PenIRQ_n='1' else ts_PenIRQ_n;

--

--lcd_red: OBUFDS

--   generic map (

--      IOSTANDARD => "DEFAULT")

--   port map (

--      o  => o_disp_a0_p,

--      ob => o_disp_a0_n,

--      i  => serdes_r );

--

--lcd_green: OBUFDS

--   generic map (

--      IOSTANDARD => "DEFAULT")

--   port map (

--      o  => o_disp_a1_p,

--      ob => o_disp_a1_n,

--      i  => serdes_g );

--

--lcd_blue: OBUFDS

--   generic map (

--      IOSTANDARD => "DEFAULT")

--   port map (

--      o  => o_disp_a2_p,

--      ob => o_disp_a2_n,

--      i  => serdes_b );

--

--lcd_ctl: OBUFDS

--   generic map (

--      IOSTANDARD => "DEFAULT")

--   port map (

--      o  => o_disp_a3_p,

--      ob => o_disp_a3_n,

--      i  => serdes_ctl );

--

--lcd_shclk: OBUFDS

--   generic map (

--      IOSTANDARD => "DEFAULT")

--   port map (

--      o  => o_disp_clkin_p,

--      ob => o_disp_clkin_n,

--      i  => serdes_clk );

--

--io_sda <= 'Z';

--o_scl  <= 'Z';

--o_dvi_hsync <= 'Z';

--o_dvi_vsync <= 'Z';

--o_dvi_de <= 'Z';

--o_dvi_clk <= 'Z';

--

--DDR2_NULL : for i in 0 to 15 generate

--begin

--    o_dvi_data(i) <= 'Z';

--end generate DDR2_NULL;

--

--end generate gen_disp;

--

--gen_dvi : if DISP_CONFIG = "DVI" generate 

--begin

--

--rev_ab : if BOARD_REV = "A" or BOARD_REV = "B" generate

--begin

--i2cctrl : i2c 

--   generic map (

--      CLK_DIVIDE => 256,

--      BYTES_PER_PAGE => 32,

--      WRITE_DLY_CNT_BIT => 10

--   )

--   Port Map ( 

--      clk            => ema_clk,

--      i_ABus         => addr_r,

--      i_DBus         => edi_r,

--      o_DBus         => edo_arm(CORE_I2C_MODULE),

--      i_wr_en        => wr_r,

--      i_rd_en        => rd_r,

--      i_cs           => arm_cs5_r(CORE_I2C_MODULE),

--      o_irq          => irq_map(CORE_I2C_IRQ_LEVEL)(CORE_I2C_IRQ_VECTOR),

--      i_ilevel       => conv_std_logic_vector(CORE_I2C_IRQ_LEVEL, 2),

--      i_ivector      => conv_std_logic_vector(CORE_I2C_IRQ_VECTOR, 4),

--      i_sda          => io_sda,

--      o_sda          => sda,

--      o_sdt          => t_sda,

--      o_scl          => o_scl

--   );

--   

--io_sda <= 'Z' when t_sda = '1' else sda;

--

--dvi :  tfp410 

--   port map (

--      ema_clk        => ema_clk,

--      i_ABus         => addr_r,

--      i_DBus         => edi_r,

--      o_DBus         => edo_arm(CORE_DVI_MODULE),

--      i_wr_en        => wr_r,

--      i_rd_en        => rd_r,

--      i_cs           => arm_cs5_r(CORE_DVI_MODULE),

--      o_irq          => irq_map(CORE_DVI_IRQ_LEVEL)(CORE_DVI_IRQ_VECTOR),

--      i_ilevel       => conv_std_logic_vector(CORE_DVI_IRQ_LEVEL, 2),

--      i_ivector      => conv_std_logic_vector(CORE_DVI_IRQ_VECTOR, 4),

--

--      -- LCD Controller interface (from OMAP-L138)

--      i_lcd_d       => i_lcd_d,

--      i_lcd_hsync   => i_lcd_hsync,

--      i_lcd_vsync   => i_lcd_vsync,

--      i_lcd_mclk    => i_lcd_mclk,

--      i_lcd_pclk    => lcd_pclk,

--      i_lcd_enb     => i_lcd_enb,

--            

--      -- DVI video interface (we assume double data rate interface for pin reduction)

--      -- these should be hooked up to the ODDR2 macro...

--      o_dvi_data_c0 => dvi_data_c0,

--      o_dvi_data_c1 => dvi_data_c1,

--      o_dvi_clk     => dvi_clk,

--      o_dvi_hsync   => o_dvi_hsync,

--      o_dvi_vsync   => o_dvi_vsync,

--      o_dvi_de      => o_dvi_de

--            

--      );

--

--DDR2 : for i in 0 to 11 generate

--begin

--

--ODDR2_inst : ODDR2

--   generic map (

--      DDR_ALIGNMENT => "NONE",

--      INIT => '0',

--      SRTYPE => "SYNC" )

--   port map (

--      Q  => o_dvi_data(i),

--      C0 => dvi_clk,

--      C1 => not dvi_clk,

--      CE => '1',

--      D0 => dvi_data_c0(i),

--      D1 => dvi_data_c1(i),

--      R  => '0',

--      S  => '0' );

--

--end generate DDR2;

--

--ODDR2_inst_clk : ODDR2

--   generic map (

--      DDR_ALIGNMENT => "NONE",

--      INIT => '0',

--      SRTYPE => "SYNC" )

--   port map (

--      Q  => o_dvi_clk,

--      C0 => dvi_clk,

--      C1 => not dvi_clk,

--      CE => '1',

--      D0 => '1',

--      D1 => '0',

--      R  => '0',

--      S  => '0' );

--

--end generate rev_ab;

--

--rev_c : if BOARD_REV = "C" generate

--begin

--

--latch_proc : process(lcd_pclk)

--begin

--    if rising_edge(lcd_pclk) then

--      o_dvi_data     <= i_lcd_d;

--      o_dvi_hsync    <= i_lcd_hsync;

--      o_dvi_vsync    <= i_lcd_vsync;

--      o_dvi_de       <= i_lcd_enb;

--    end if;

--end process latch_proc;

--

--o_dvi_clk <= not lcd_pclk;

--io_sda <= 'Z';

--o_scl  <= 'Z';

--

--end generate rev_c;

--

--o_ts_cs_n     <= 'Z';

--o_ts_clk      <= 'Z';

--o_ts_din      <= 'Z';

--io_ts_PenIRQ_n <= 'Z';

--o_disp_cs_n   <= 'Z';

--o_disp_a0_p   <= 'Z';

--o_disp_a0_n   <= 'Z';

--o_disp_a1_p   <= 'Z';

--o_disp_a1_n   <= 'Z';

--o_disp_a2_p   <= 'Z';

--o_disp_a2_n   <= 'Z';

--o_disp_a3_p   <= 'Z';

--o_disp_a3_n   <= 'Z';

--o_disp_clkin_p   <= 'Z';

--o_disp_clkin_n   <= 'Z';

--

--end generate gen_dvi;

--

--gen_camera : if CAMERA_CONFIG = "RAW" generate

--begin

--

--cam_clk_bufg : bufg Port Map (I => i_cam_pclk, O => cam_pclk);

--

--latch_cam_data : process(cam_pclk)

--begin

--    if rising_edge(cam_pclk) then

--        cam_data <= i_cam_data;

--        cam_lv   <= i_cam_lv;

--        cam_fv   <= i_cam_fv;

--    end if;

--end process;

--

--o_vp_clkin(0)   <= cam_pclk;

--o_vp_clkin(1)   <= cam_pclk;

--o_vp_hsync    <= cam_lv;

--o_vp_vsync    <= cam_fv;

--o_vp_field    <= '0';

--o_vp_din      <= "000" & cam_data;

--

--pwm1 : pwm 

--	generic map (

--	    NUM_OUTPUTS => 2

--	)

--	Port Map (

--      emif_clk       => ema_clk,

--      i_ABus         => addr_r,

--      i_DBus         => edi_r,

--      o_DBus         => edo_arm(CORE_PWM_MODULE),

--      i_wr_en        => wr_r,

--      i_rd_en        => rd_r,

--      i_cs           => arm_cs5_r(CORE_PWM_MODULE),

--      o_irq          => irq_map(CORE_PWM_IRQ_LEVEL)(CORE_PWM_IRQ_VECTOR),

--      i_ilevel       => conv_std_logic_vector(CORE_PWM_IRQ_LEVEL, 2),

--      i_ivector      => conv_std_logic_vector(CORE_PWM_IRQ_VECTOR, 4),

--	   o_pwm(1 downto 0) => o_pwm,

--		o_sync         => open,