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/*
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* mux.c
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*
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <config.h>
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#include "common_def.h"
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#include <asm/arch/hardware.h>
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#include <asm/arch/mux.h>
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#define DEV_ON_BASEBOARD 0
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#define DEV_ON_DGHTR_BRD 1
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struct evm_pin_mux {
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struct module_pin_mux *mod_pin_mux;
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unsigned short profile;
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};
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static struct module_pin_mux uart0_pin_mux[] = {
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{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
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{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
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{-1},
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};
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#ifdef CONFIG_NAND
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static struct module_pin_mux nand_pin_mux[] = {
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{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
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{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
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{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
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{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
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{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
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{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
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{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
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{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
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{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
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{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
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{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
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{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
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{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
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{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
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{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
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{-1},
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};
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#endif
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static struct module_pin_mux i2c0_pin_mux[] = {
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{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
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{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
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{-1},
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};
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static struct module_pin_mux i2c1_pin_mux[] = {
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{OFFSET(mii1_crs), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
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{OFFSET(mii1_rxerr), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
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{-1},
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};
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static struct module_pin_mux i2c2_pin_mux[] = {
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{OFFSET(uart1_ctsn), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
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{OFFSET(uart1_rtsn), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
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{-1},
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};
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#ifndef CONFIG_NO_ETH
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static struct module_pin_mux rgmii1_pin_mux[] = {
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{OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
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{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
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{OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
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{OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
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{OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
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{OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
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{OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
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{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
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{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
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{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
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{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
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{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
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{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
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{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
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{-1},
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};
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static struct module_pin_mux rgmii2_pin_mux[] = {
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{OFFSET(gpmc_a0), MODE(2)}, /* RGMII2_TCTL */
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{OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII2_RCTL */
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{OFFSET(gpmc_a2), MODE(2)}, /* RGMII2_TD3 */
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{OFFSET(gpmc_a3), MODE(2)}, /* RGMII2_TD2 */
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{OFFSET(gpmc_a4), MODE(2)}, /* RGMII2_TD1 */
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{OFFSET(gpmc_a5), MODE(2)}, /* RGMII2_TD0 */
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{OFFSET(gpmc_a6), MODE(2)}, /* RGMII2_TCLK */
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{OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII2_RCLK */
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{OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII2_RD3 */
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{OFFSET(gpmc_a9), MODE(2) | RXACTIVE}, /* RGMII2_RD2 */
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{OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII2_RD1 */
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{OFFSET(gpmc_a11), MODE(2) | RXACTIVE}, /* RGMII2_RD0 */
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{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
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{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
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{OFFSET(mii1_rxclk), MODE(7) | PULLUP_EN | PULLUDEN}, /* PHY RESET N on MITYARM3359 EVM */
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{-1},
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};
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// UNUSED
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//static struct module_pin_mux mii1_pin_mux[] = {
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// {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
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// {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
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// {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
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// {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
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// {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
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// {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
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// {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
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// {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
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// {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
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// {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
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// {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
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// {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
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// {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
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// {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
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// {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
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// {-1},
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//};
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//
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//static struct module_pin_mux rmii1_pin_mux[] = {
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// {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */
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// {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
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// {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
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// {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
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// {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
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// {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
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// {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
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// {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
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// {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
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// {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
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// {-1},
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//};
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#endif
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#ifdef CONFIG_MMC
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static struct module_pin_mux mmc0_pin_mux[] = {
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{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
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{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
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{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
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{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
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{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
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{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
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#ifndef CONFIG_AM335X_TF
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{OFFSET(mii1_col), (MODE(7) | RXACTIVE)}, /* MMC0_WP */
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{OFFSET(mii1_txen), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
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#endif /* CONFIG_AM335X_TF */
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{-1},
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};
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// UNUSED
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//static struct module_pin_mux mmc1_pin_mux[] = {
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// {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE)}, /* MMC1_DAT3 */
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// {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE)}, /* MMC1_DAT2 */
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// {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE)}, /* MMC1_DAT1 */
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// {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE)}, /* MMC1_DAT0 */
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// {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
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// {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
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// {OFFSET(uart1_rxd), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
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// {OFFSET(mcasp0_fsx), (MODE(4) | RXACTIVE)}, /* MMC1_CD */
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// {-1},
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//};
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#endif
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#ifdef CONFIG_SPI
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static struct module_pin_mux spi0_pin_mux[] = {
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{OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE}, /*SPI0_SCLK */
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{OFFSET(spi0_d0), MODE(0) | PULLUDEN | PULLUP_EN |
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RXACTIVE}, /*SPI0_D0 */
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{OFFSET(spi0_d1), MODE(0) | PULLUDEN |
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RXACTIVE}, /*SPI0_D1 */
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{OFFSET(spi0_cs0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE}, /*SPI0_CS0 */
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{-1},
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};
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static struct module_pin_mux spi1_pin_mux[] = {
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{OFFSET(ecap0_in_pwm0_out), MODE(4) | PULLUDEN | RXACTIVE}, /*SPI1_SCLK */
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{OFFSET(mcasp0_fsx), MODE(3) | PULLUDEN | PULLUP_EN |
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RXACTIVE}, /*SPI1_D0 */
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{OFFSET(mcasp0_axr0), MODE(3) | PULLUDEN | RXACTIVE}, /*SPI1_D1 */
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{OFFSET(mcasp0_ahclkr), MODE(3) | PULLUDEN | PULLUP_EN |
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RXACTIVE}, /*SPI1_CS0 */
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{-1},
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};
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#endif
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/*
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* Update the structure with the modules present in the general purpose
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* board and the profiles in which the modules are present.
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* If the module is physically present but if it is not available
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* in any of the profile, then do not update it.
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* For eg, nand is avialable only in the profiles 0 and 1, whereas
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* UART0 is available in all the profiles.
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*/
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static struct evm_pin_mux general_purpose_evm_pin_mux[] = {
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{uart0_pin_mux, PROFILE_ALL},
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{i2c1_pin_mux, PROFILE_ALL},
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{i2c2_pin_mux, PROFILE_ALL},
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#ifdef CONFIG_NAND
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{nand_pin_mux, PROFILE_ALL},
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#endif
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#ifndef CONFIG_NO_ETH
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{rgmii1_pin_mux, PROFILE_1},
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{rgmii2_pin_mux, PROFILE_0},
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#endif
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#ifdef CONFIG_MMC
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{mmc0_pin_mux, PROFILE_ALL},
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// {mmc1_pin_mux, PROFILE_2},
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#endif
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#ifdef CONFIG_SPI
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{spi0_pin_mux, PROFILE_0},
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{spi1_pin_mux, PROFILE_0},
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#endif
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{0},
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};
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230
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static struct evm_pin_mux *am335x_pin_mux[] = {
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general_purpose_evm_pin_mux,
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};
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234
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/*
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* Check each module in the daughter board(first argument) whether it is
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* available in the selected profile(second argument). If the module is not
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* available in the selected profile, skip the corresponding configuration.
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*/
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static void set_evm_pin_mux(struct evm_pin_mux *pin_mux,
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int prof)
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{
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int i;
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244
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if (!pin_mux)
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return;
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247
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for (i = 0; pin_mux[i].mod_pin_mux != 0; i++) {
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if ((pin_mux[i].profile & prof) ||
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(prof == PROFILE_NONE)) {
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configure_module_pin_mux(pin_mux[i].
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mod_pin_mux);
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}
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}
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255
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}
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256
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257
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void configure_evm_pin_mux(unsigned char profile)
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258
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{
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set_evm_pin_mux(am335x_pin_mux[0], profile);
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}
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void enable_mmc0_pin_mux(void)
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{
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264
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#ifdef CONFIG_MMC
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configure_module_pin_mux(mmc0_pin_mux);
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#endif
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}
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void enable_i2c0_pin_mux(void)
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{
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270
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configure_module_pin_mux(i2c0_pin_mux);
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271
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}
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272
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273
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void enable_i2c1_pin_mux(void)
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274
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{
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275
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configure_module_pin_mux(i2c1_pin_mux);
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}
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277
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void enable_i2c2_pin_mux(void)
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278
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{
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279
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configure_module_pin_mux(i2c2_pin_mux);
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280
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}
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281
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282
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void enable_uart0_pin_mux(void)
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283
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{
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284
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configure_module_pin_mux(uart0_pin_mux);
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}
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