RE: Ethernet RMII2 working in u-boot, but not kernel ยป skyline-0002-sent-to-criticallink-for-review.patch
| arch/arm/mach-omap2/baseboard-mityarm335x-devkit.c | ||
|---|---|---|
| 80 | 80 |
* |
| 81 | 81 |
*****************************************************************************/ |
| 82 | 82 | |
| 83 |
static struct pinmux_config rmii2_pin_mux[] = {
|
|
| 84 |
{"gpmc_csn3.rmii2_crs_dv", AM33XX_PIN_INPUT_PULLUP},
|
|
| 85 |
// {"gpmc_wait0.rmii2_crs_dv", AM33XX_PIN_INPUT_PULLUP},
|
|
| 86 |
{"gpmc_a0.rmii2_txen", AM33XX_PIN_OUTPUT}, // --
|
|
| 87 |
{"gpmc_a5.rmii2_txd0", AM33XX_PIN_OUTPUT}, // --
|
|
| 88 |
{"gpmc_a4.rmii2_txd1", AM33XX_PIN_OUTPUT}, // ---
|
|
| 89 |
{"gpmc_a11.rmii2_rxd0", AM33XX_PIN_INPUT_PULLDOWN}, // --
|
|
| 90 |
{"gpmc_a10.rmii2_rxd1", AM33XX_PIN_INPUT_PULLDOWN}, // --
|
|
| 91 |
{"mii1_col.rmii2_refclk", AM33XX_PIN_INPUT_PULLDOWN}, // --
|
|
| 92 |
{"mdio_data.mdio_data", AM33XX_PIN_INPUT_PULLUP},
|
|
| 93 |
{"mdio_clk.mdio_clk", AM33XX_PIN_OUTPUT_PULLUP},
|
|
| 94 |
{NULL, 0}
|
|
| 95 |
}; |
|
| 83 | 96 |
static struct pinmux_config rgmii2_pin_mux[] = {
|
| 84 | 97 |
{"gpmc_a0.rgmii2_tctl", AM33XX_PIN_OUTPUT},
|
| 85 | 98 |
{"gpmc_a1.rgmii2_rctl", AM33XX_PIN_INPUT_PULLDOWN},
|
| ... | ... | |
| 99 | 112 |
}; |
| 100 | 113 | |
| 101 | 114 |
static struct pinmux_config lcdc_pin_mux[] = {
|
| 115 |
#if 0 //danm |
|
| 102 | 116 |
{"lcd_data0.lcd_data0", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
|
| 103 | 117 |
{"lcd_data1.lcd_data1", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
|
| 104 | 118 |
{"lcd_data2.lcd_data2", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
|
| ... | ... | |
| 121 | 135 |
{"lcd_ac_bias_en.lcd_ac_bias_en", AM33XX_PIN_OUTPUT},
|
| 122 | 136 |
/* GPIO for the backlight */ |
| 123 | 137 |
{ "mcasp0_aclkx.gpio3_14", AM33XX_PIN_OUTPUT},
|
| 138 |
#endif |
|
| 124 | 139 |
{NULL, 0}
|
| 125 | 140 |
}; |
| 126 | 141 | |
| ... | ... | |
| 131 | 146 |
{"mmc0_dat0.mmc0_dat0", AM33XX_PIN_INPUT_PULLUP},
|
| 132 | 147 |
{"mmc0_clk.mmc0_clk", AM33XX_PIN_INPUT_PULLUP},
|
| 133 | 148 |
{"mmc0_cmd.mmc0_cmd", AM33XX_PIN_INPUT_PULLUP},
|
| 134 |
{"mii1_txen.gpio3_3", AM33XX_PIN_INPUT_PULLUP}, /* SD Card Detect */
|
|
| 135 |
{"mii1_col.gpio3_0", AM33XX_PIN_INPUT_PULLUP}, /* SD Write Protect */
|
|
| 149 |
// danm {"mii1_txen.gpio3_3", AM33XX_PIN_INPUT_PULLUP}, /* SD Card Detect */
|
|
| 150 |
// {"mii1_col.gpio3_0", AM33XX_PIN_INPUT_PULLUP}, /* SD Write Protect */
|
|
| 136 | 151 |
{NULL, 0}
|
| 137 | 152 |
}; |
| 138 | 153 | |
| ... | ... | |
| 167 | 182 |
}; |
| 168 | 183 | |
| 169 | 184 |
static struct pinmux_config expansion_pin_mux[] = {
|
| 170 |
{"uart0_ctsn.uart4_rxd", AM33XX_PIN_INPUT_PULLUP},/* Exp0 RX */
|
|
| 171 |
{"uart0_rtsn.uart4_txd", AM33XX_PULL_ENBL}, /* Exp0 TX */
|
|
| 172 |
{"mii1_rxd3.uart3_rxd", AM33XX_PIN_INPUT_PULLUP},/* Exp1 RX */
|
|
| 173 |
{"mii1_rxd2.uart3_txd", AM33XX_PULL_ENBL}, /* Exp1 TX */
|
|
| 174 |
{"mii1_rxd1.gpio2_20", AM33XX_PULL_ENBL}, /* Exp1 TX EN */
|
|
| 175 |
{"mii1_txclk.gpio3_9", AM33XX_PULL_ENBL}, /* Exp0 TX EN */
|
|
| 185 |
{"uart1_rxd.uart1_rxd", AM33XX_PIN_INPUT_PULLUP},/* Exp0 RX */
|
|
| 186 |
{"uart1_txd.uart1_txd", AM33XX_PULL_ENBL}, /* Exp0 TX */
|
|
| 187 |
{"mii1_rxd3.uart1_dtrn", AM33XX_PULL_ENBL}, /* uart 1 modem */
|
|
| 188 |
{"mii1_rxclk..uart1_dsrn", AM33XX_PULL_ENBL}, /* */
|
|
| 189 |
{"mii1_txclk.uart1_dcdn", AM33XX_PULL_ENBL}, /* */
|
|
| 190 | ||
| 191 |
{"spi0_sclk.uart2_rxd", AM33XX_PIN_INPUT_PULLUP},/* Exp0 RX */
|
|
| 192 |
{"spi0_d0.uart2_txd", AM33XX_PULL_ENBL}, /* Exp0 TX */
|
|
| 193 | ||
| 194 |
{"spi0_cs1.uart3_rxd", AM33XX_PIN_INPUT_PULLUP},/*- Exp0 RX */
|
|
| 195 |
{"mii1_rxd2.uart3_txd", AM33XX_PULL_ENBL}, /* - Exp0 TX */
|
|
| 196 | ||
| 197 |
{"mii1_txd3.uart4_rxd", AM33XX_PIN_INPUT_PULLUP},/* - Exp0 RX */
|
|
| 198 |
{"mii1_txd2.uart4_txd", AM33XX_PULL_ENBL}, /* Exp0 TX */
|
|
| 199 | ||
| 200 |
{"lcd_data9.uart5_rxd", AM33XX_PIN_INPUT_PULLUP},/*- Exp0 RX */
|
|
| 201 |
{"lcd_data8.uart5_txd", AM33XX_PULL_ENBL}, /*- Exp0 TX */
|
|
| 176 | 202 |
{NULL, 0}
|
| 177 | 203 |
}; |
| 178 | 204 | |
| 205 | ||
| 179 | 206 |
static struct pinmux_config usb_pin_mux[] = {
|
| 180 | 207 |
{"usb0_drvvbus.usb0_drvvbus", AM33XX_PIN_OUTPUT},
|
| 181 | 208 |
{"usb1_drvvbus.usb1_drvvbus", AM33XX_PIN_OUTPUT},
|
| ... | ... | |
| 250 | 277 |
{
|
| 251 | 278 |
.mmc = 1, |
| 252 | 279 |
.caps = MMC_CAP_4_BIT_DATA, |
| 253 |
.gpio_cd = GPIO_TO_PIN(3, 3),
|
|
| 254 |
.gpio_wp = GPIO_TO_PIN(3, 0),
|
|
| 280 |
.gpio_cd = -EINVAL, // GPIO_TO_PIN(3, 3),
|
|
| 281 |
.gpio_wp = -EINVAL, //GPIO_TO_PIN(3, 0),
|
|
| 255 | 282 |
.ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, |
| 256 | 283 |
}, |
| 257 | 284 |
{
|
| ... | ... | |
| 580 | 607 |
static __init void baseboard_setup_enet(void) |
| 581 | 608 |
{
|
| 582 | 609 |
/* pinmux */ |
| 583 |
setup_pin_mux(rgmii2_pin_mux);
|
|
| 610 |
setup_pin_mux(rmii2_pin_mux);
|
|
| 584 | 611 | |
| 585 | 612 |
/* network configuration done in SOM code */ |
| 586 | 613 |
/* PHY address setup? */ |
| arch/arm/mach-omap2/board-mityarm335x.c | ||
|---|---|---|
| 517 | 517 |
am33xx_mux_init(NULL); |
| 518 | 518 |
omap_serial_init(); |
| 519 | 519 |
am335x_rtc_init(); |
| 520 |
am33xx_cpsw_init(1); /* 1 == enable gigabit */
|
|
| 520 |
am33xx_cpsw_init(0); /* 1 == enable gigabit */
|
|
| 521 | 521 |
mityarm335x_i2c_init(); |
| 522 | 522 |
omap_sdrc_init(NULL, NULL); |
| 523 | 523 |
spi1_init(); |
| arch/arm/mach-omap2/devices.c | ||
|---|---|---|
| 1139 | 1139 |
#ifdef CONFIG_BASEBOARD_MITYARM335X_TESTFIXTURE |
| 1140 | 1140 |
.phy_id = "0:01", |
| 1141 | 1141 |
#else |
| 1142 |
.phy_id = "0:00",
|
|
| 1142 |
.phy_id = "0:01",
|
|
| 1143 | 1143 |
#endif |
| 1144 | 1144 | |
| 1145 | 1145 |
}, |
| ... | ... | |
| 1149 | 1149 |
#ifdef CONFIG_BASEBOARD_MITYARM335X_TESTFIXTURE |
| 1150 | 1150 |
.phy_id = "0:00", |
| 1151 | 1151 |
#else |
| 1152 |
.phy_id = "0:01",
|
|
| 1152 |
.phy_id = "0:00",
|
|
| 1153 | 1153 |
#endif |
| 1154 | 1154 |
}, |
| 1155 | 1155 |
}; |
| ... | ... | |
| 1168 | 1168 |
.bd_ram_size = SZ_16K, |
| 1169 | 1169 |
.rx_descs = 64, |
| 1170 | 1170 |
.mac_control = BIT(5), /* MIIEN */ |
| 1171 |
.gigabit_en = 1,
|
|
| 1171 |
.gigabit_en = 0,
|
|
| 1172 | 1172 |
.host_port_num = 0, |
| 1173 | 1173 |
.no_bd_ram = false, |
| 1174 | 1174 |
.version = CPSW_VERSION_2, |
| ... | ... | |
| 1324 | 1324 | |
| 1325 | 1325 |
am33xx_cpsw_pdata.gigabit_en = gigen; |
| 1326 | 1326 | |
| 1327 | ||
| 1327 | 1328 |
memcpy(am33xx_cpsw_pdata.mac_addr, |
| 1328 | 1329 |
am33xx_cpsw_slaves[0].mac_addr, ETH_ALEN); |
| 1329 | 1330 |
platform_device_register(&am33xx_cpsw_mdiodevice); |
| 1330 | 1331 |
platform_device_register(&am33xx_cpsw_device); |
| 1332 | ||
| 1333 |
#define MII_MODE_ENABLE 0x0 |
|
| 1334 |
#define RMII_MODE_ENABLE 0x4 //5 |
|
| 1335 |
#define RGMII_MODE_ENABLE 0xA |
|
| 1336 |
#define MAC_MII_SEL 0x650 |
|
| 1337 |
#define SMA2_ADDR 0x1320 |
|
| 1338 | ||
| 1339 |
__raw_writel(RMII_MODE_ENABLE | 0xb0, //danm |
|
| 1340 |
AM33XX_CTRL_REGADDR(MAC_MII_SEL)); |
|
| 1341 | ||
| 1342 |
__raw_writel(0x0, //danm |
|
| 1343 |
AM33XX_CTRL_REGADDR(SMA2_ADDR)); |
|
| 1344 |
printk("%s gmii_sel 0x%x\n",__func__,
|
|
| 1345 |
__raw_readl(AM33XX_CTRL_REGADDR(MAC_MII_SEL))); //danm |
|
| 1346 | ||
| 1347 | ||
| 1348 | ||
| 1349 | ||
| 1331 | 1350 |
clk_add_alias(NULL, dev_name(&am33xx_cpsw_mdiodevice.dev), |
| 1332 | 1351 |
NULL, &am33xx_cpsw_device.dev); |
| 1333 | 1352 |
} |
| arch/arm/mach-omap2/mux33xx.c | ||
|---|---|---|
| 1 | ||
| 2 | ||
| 1 | 3 |
/* |
| 2 | 4 |
* AM33XX mux data |
| 3 | 5 |
* |
| ... | ... | |
| 31 | 33 |
static struct omap_mux __initdata am33xx_muxmodes[] = {
|
| 32 | 34 |
_AM33XX_MUXENTRY(GPMC_AD0, 0, |
| 33 | 35 |
"gpmc_ad0", "mmc1_dat0", NULL, NULL, |
| 34 |
NULL, NULL, NULL, NULL), |
|
| 36 |
NULL, NULL, NULL, "gpio1_0"), // danm |
|
| 35 | 37 |
_AM33XX_MUXENTRY(GPMC_AD1, 0, |
| 36 | 38 |
"gpmc_ad1", "mmc1_dat1", NULL, NULL, |
| 37 |
NULL, NULL, NULL, NULL),
|
|
| 39 |
NULL, NULL, NULL, "gpio1_1"),
|
|
| 38 | 40 |
_AM33XX_MUXENTRY(GPMC_AD2, 0, |
| 39 | 41 |
"gpmc_ad2", "mmc1_dat2", NULL, NULL, |
| 40 |
NULL, NULL, NULL, NULL),
|
|
| 42 |
NULL, NULL, NULL, "gpio1_2"),
|
|
| 41 | 43 |
_AM33XX_MUXENTRY(GPMC_AD3, 0, |
| 42 | 44 |
"gpmc_ad3", "mmc1_dat3", NULL, NULL, |
| 43 |
NULL, NULL, NULL, NULL),
|
|
| 45 |
NULL, NULL, NULL, "gpio1_3"),
|
|
| 44 | 46 |
_AM33XX_MUXENTRY(GPMC_AD4, 0, |
| 45 | 47 |
"gpmc_ad4", "mmc1_dat4", NULL, NULL, |
| 46 |
NULL, NULL, NULL, NULL),
|
|
| 48 |
NULL, NULL, NULL, "gpio1_4"),
|
|
| 47 | 49 |
_AM33XX_MUXENTRY(GPMC_AD5, 0, |
| 48 | 50 |
"gpmc_ad5", "mmc1_dat5", NULL, NULL, |
| 49 |
NULL, NULL, NULL, NULL),
|
|
| 51 |
NULL, NULL, NULL, "gpio1_5"),
|
|
| 50 | 52 |
_AM33XX_MUXENTRY(GPMC_AD6, 0, |
| 51 | 53 |
"gpmc_ad6", "mmc1_dat6", NULL, NULL, |
| 52 |
NULL, NULL, NULL, NULL),
|
|
| 54 |
NULL, NULL, NULL, "gpio1_6"),
|
|
| 53 | 55 |
_AM33XX_MUXENTRY(GPMC_AD7, 0, |
| 54 | 56 |
"gpmc_ad7", "mmc1_dat7", NULL, NULL, |
| 55 |
NULL, NULL, NULL, NULL),
|
|
| 57 |
NULL, NULL, NULL, "gpio1_7"),
|
|
| 56 | 58 |
_AM33XX_MUXENTRY(GPMC_AD8, 0, |
| 57 | 59 |
"gpmc_ad8", "lcd_data16", "mmc1_dat0", "mmc2_dat4", |
| 58 | 60 |
NULL, NULL, NULL, "gpio0_22"), |
| 59 | 61 |
_AM33XX_MUXENTRY(GPMC_AD9, 0, |
| 60 | 62 |
"gpmc_ad9", "lcd_data17", "mmc1_dat1", "mmc2_dat5", |
| 61 |
NULL, NULL, NULL, "gpio0_23"),
|
|
| 63 |
"ehrpwm2B", NULL, NULL, "gpio0_23"),
|
|
| 62 | 64 |
_AM33XX_MUXENTRY(GPMC_AD10, 0, |
| 63 | 65 |
"gpmc_ad10", "lcd_data18", "mmc1_dat2", "mmc2_dat6", |
| 64 | 66 |
NULL, NULL, NULL, "gpio0_26"), |
| ... | ... | |
| 115 | 117 |
NULL, NULL, "mcasp0_axr1", "gpio1_27"), |
| 116 | 118 |
_AM33XX_MUXENTRY(GPMC_WAIT0, 0, |
| 117 | 119 |
"gpmc_wait0", "mii2_crs", NULL, "rmii2_crs_dv", |
| 118 |
"mmc1_sdcd", NULL, NULL, NULL),
|
|
| 120 |
"mmc1_sdcd", NULL, NULL, "gpio0_30"),
|
|
| 119 | 121 |
_AM33XX_MUXENTRY(GPMC_WPN, 0, |
| 120 | 122 |
"gpmc_wpn", "mii2_rxerr", NULL, "rmii2_rxerr", |
| 121 |
"mmc2_sdcd", NULL, NULL, NULL),
|
|
| 123 |
"mmc2_sdcd", NULL, NULL, "gpio0_31"),
|
|
| 122 | 124 |
_AM33XX_MUXENTRY(GPMC_BEN1, 0, |
| 123 | 125 |
"gpmc_ben1", "mii2_col", NULL, "mmc2_dat3", |
| 124 | 126 |
NULL, NULL, "mcasp0_aclkr", "gpio1_28"), |
| 125 | 127 |
_AM33XX_MUXENTRY(GPMC_CSN0, 0, |
| 126 | 128 |
"gpmc_csn0", NULL, NULL, NULL, |
| 127 |
NULL, NULL, NULL, "mmc1_sdwp"),
|
|
| 129 |
NULL, NULL, NULL, "gpio1_29"),
|
|
| 128 | 130 |
_AM33XX_MUXENTRY(GPMC_CSN1, 0, |
| 129 | 131 |
"gpmc_csn1", NULL, "mmc1_clk", NULL, |
| 130 | 132 |
NULL, NULL, NULL, "gpio1_30"), |
| ... | ... | |
| 132 | 134 |
"gpmc_csn2", NULL, "mmc1_cmd", NULL, |
| 133 | 135 |
NULL, NULL, NULL, "gpio1_31"), |
| 134 | 136 |
_AM33XX_MUXENTRY(GPMC_CSN3, 0, |
| 135 |
"gpmc_csn3", NULL, NULL, "mmc2_cmd",
|
|
| 137 |
"gpmc_csn3", NULL, "rmii2_crs_dv", "mmc2_cmd",
|
|
| 136 | 138 |
NULL, NULL, NULL, "gpio2_0"), |
| 137 | 139 |
_AM33XX_MUXENTRY(GPMC_CLK, 0, |
| 138 | 140 |
"gpmc_clk", "lcd_memory_clk_mux", NULL, "mmc2_clk", |
| ... | ... | |
| 142 | 144 |
NULL, NULL, NULL, "mmc1_sdcd"), |
| 143 | 145 |
_AM33XX_MUXENTRY(GPMC_OEN_REN, 0, |
| 144 | 146 |
"gpmc_oen_ren", NULL, NULL, NULL, |
| 145 |
NULL, NULL, NULL, NULL),
|
|
| 147 |
NULL, NULL, NULL, "gpio2_3"),
|
|
| 146 | 148 |
_AM33XX_MUXENTRY(GPMC_WEN, 0, |
| 147 | 149 |
"gpmc_wen", NULL, NULL, NULL, |
| 148 |
NULL, NULL, NULL, NULL),
|
|
| 150 |
NULL, NULL, NULL, "gpio2_4"),
|
|
| 149 | 151 |
_AM33XX_MUXENTRY(GPMC_BEN0_CLE, 0, |
| 150 | 152 |
"gpmc_ben0_cle", NULL, NULL, NULL, |
| 151 |
NULL, NULL, NULL, NULL),
|
|
| 153 |
NULL, NULL, NULL, "gpio2_5"),
|
|
| 152 | 154 |
_AM33XX_MUXENTRY(LCD_DATA0, 0, |
| 153 | 155 |
"lcd_data0", "gpmc_a0", NULL, NULL, |
| 154 | 156 |
NULL, NULL, NULL, "gpio2_6"), |
| ... | ... | |
| 175 | 177 |
NULL, NULL, NULL, "gpio2_13"), |
| 176 | 178 |
_AM33XX_MUXENTRY(LCD_DATA8, 0, |
| 177 | 179 |
"lcd_data8", "gpmc_a12", NULL, "mcasp0_aclkx", |
| 178 |
NULL, NULL, "uart2_ctsn", "gpio2_14"),
|
|
| 180 |
"uart5_txd", NULL, "uart2_ctsn", "gpio2_14"),
|
|
| 179 | 181 |
_AM33XX_MUXENTRY(LCD_DATA9, 0, |
| 180 | 182 |
"lcd_data9", "gpmc_a13", NULL, "mcasp0_fsx", |
| 181 |
NULL, NULL, "uart2_rtsn", "gpio2_15"),
|
|
| 183 |
"uart5_rxd", NULL, "uart2_rtsn", "gpio2_15"),
|
|
| 182 | 184 |
_AM33XX_MUXENTRY(LCD_DATA10, 0, |
| 183 | 185 |
"lcd_data10", "gpmc_a14", NULL, "mcasp0_axr0", |
| 184 | 186 |
NULL, NULL, NULL, "gpio2_16"), |
| ... | ... | |
| 221 | 223 |
_AM33XX_MUXENTRY(MMC0_DAT0, 0, |
| 222 | 224 |
"mmc0_dat0", NULL, NULL, NULL, |
| 223 | 225 |
NULL, NULL, NULL, "gpio2_29"), |
| 224 |
_AM33XX_MUXENTRY(MMC0_CLK, 0, |
|
| 225 |
"mmc0_clk", NULL, NULL, NULL,
|
|
| 226 |
_AM33XX_MUXENTRY(MMC0_CLK, 0, // skyline danm |
|
| 227 |
"mmc0_clk", "gpmc_a24", "uart3_ctsn", "uart2_rxd",
|
|
| 226 | 228 |
NULL, NULL, NULL, "gpio2_30"), |
| 227 |
_AM33XX_MUXENTRY(MMC0_CMD, 0, |
|
| 228 |
"mmc0_cmd", NULL, NULL, NULL,
|
|
| 229 |
_AM33XX_MUXENTRY(MMC0_CMD, 0, // skyline danm |
|
| 230 |
"mmc0_cmd", "gpmc_a25", "uart3_rtsn", "uart2_txd",
|
|
| 229 | 231 |
NULL, NULL, NULL, "gpio2_31"), |
| 230 | 232 |
_AM33XX_MUXENTRY(MII1_COL, 0, |
| 231 | 233 |
"mii1_col", "rmii2_refclk", "spi1_sclk", NULL, |
| 232 | 234 |
"mcasp1_axr2", "mmc2_dat3", "mcasp0_axr2", "gpio3_0"), |
| 233 | 235 |
_AM33XX_MUXENTRY(MII1_CRS, 0, |
| 234 | 236 |
"mii1_crs", "rmii1_crs_dv", "spi1_d0", "i2c1_sda", |
| 235 |
"mcasp1_aclkx", NULL, NULL, NULL),
|
|
| 237 |
"mcasp1_aclkx", NULL, NULL, "gpio3_1"),
|
|
| 236 | 238 |
_AM33XX_MUXENTRY(MII1_RXERR, 0, |
| 237 | 239 |
"mii1_rxerr", "rmii1_rxerr", "spi1_d1", "i2c1_scl", |
| 238 |
"mcasp1_fsx", NULL, NULL, NULL),
|
|
| 240 |
"mcasp1_fsx", NULL, NULL, "gpio3_2"),
|
|
| 239 | 241 |
_AM33XX_MUXENTRY(MII1_TXEN, 0, |
| 240 | 242 |
"mii1_txen", "rmii1_txen", "rgmii1_tctl", NULL, |
| 241 | 243 |
"mcasp1_axr0", NULL, "mmc2_cmd", "gpio3_3"), |
| 242 | 244 |
_AM33XX_MUXENTRY(MII1_RXDV, 0, |
| 243 | 245 |
"mii1_rxdv", NULL, "rgmii1_rctl", NULL, |
| 244 |
"mcasp1_aclx", "mmc2_dat0", "mcasp0_aclkr", NULL),
|
|
| 246 |
"mcasp1_aclx", "mmc2_dat0", "mcasp0_aclkr", "gpio3_4"),
|
|
| 245 | 247 |
_AM33XX_MUXENTRY(MII1_TXD3, 0, |
| 246 |
"mii1_txd3", "d_can0_tx", "rgmii1_td3", NULL,
|
|
| 247 |
"mcasp1_fsx", "mmc2_dat1", "mcasp0_fsr", NULL),
|
|
| 248 |
"mii1_txd3", "d_can0_tx", "rgmii1_td3", "uart4_rxd",
|
|
| 249 |
"mcasp1_fsx", "mmc2_dat1", "mcasp0_fsr", "gpio0_16"),
|
|
| 248 | 250 |
_AM33XX_MUXENTRY(MII1_TXD2, 0, |
| 249 |
"mii1_txd2", "d_can0_rx", "rgmii1_td2", NULL,
|
|
| 250 |
"mcasp1_axr0", "mmc2_dat2", "mcasp0_ahclkx", NULL),
|
|
| 251 |
"mii1_txd2", "d_can0_rx", "rgmii1_td2", "uart4_txd",
|
|
| 252 |
"mcasp1_axr0", "mmc2_dat2", "mcasp0_ahclkx", "gpio0_17"),
|
|
| 251 | 253 |
_AM33XX_MUXENTRY(MII1_TXD1, 0, |
| 252 | 254 |
"mii1_txd1", "rmii1_txd1", "rgmii1_td1", "mcasp1_fsr", |
| 253 |
"mcasp1_axr1", NULL, "mmc1_cmd", NULL),
|
|
| 255 |
"mcasp1_axr1", NULL, "mmc1_cmd", "gpio0_21"),
|
|
| 254 | 256 |
_AM33XX_MUXENTRY(MII1_TXD0, 0, |
| 255 | 257 |
"mii1_txd0", "rmii1_txd0", "rgmii1_td0", "mcasp1_axr2", |
| 256 | 258 |
"mcasp1_aclkr", NULL, "mmc1_clk", "gpio0_28"), |
| 257 | 259 |
_AM33XX_MUXENTRY(MII1_TXCLK, 0, |
| 258 | 260 |
"mii1_txclk", NULL, "rgmii1_tclk", "mmc0_dat7", |
| 259 |
"mmc1_dat0", NULL, "mcasp0_aclkx", "gpio3_9"),
|
|
| 261 |
"mmc1_dat0", "uart1_dcdn", "mcasp0_aclkx", "gpio3_9"),
|
|
| 260 | 262 |
_AM33XX_MUXENTRY(MII1_RXCLK, 0, |
| 261 | 263 |
"mii1_rxclk", NULL, "rgmii1_rclk", "mmc0_dat6", |
| 262 |
"mmc1_dat1", NULL, "mcasp0_fsx", NULL),
|
|
| 264 |
"mmc1_dat1", "uart1_dsrn", "mcasp0_fsx", "gpio3_10"),
|
|
| 263 | 265 |
_AM33XX_MUXENTRY(MII1_RXD3, 0, |
| 264 | 266 |
"mii1_rxd3", "uart3_rxd", "rgmii1_rd3", "mmc0_dat5", |
| 265 | 267 |
"mmc1_dat2", "uart1_dtrn", "mcasp0_axr0", "gpio2_18"), |
| ... | ... | |
| 271 | 273 |
"mcasp1_fsr", NULL, "mmc2_clk", "gpio2_20"), |
| 272 | 274 |
_AM33XX_MUXENTRY(MII1_RXD0, 0, |
| 273 | 275 |
"mii1_rxd0", "rmii1_rxd0", "rgmii1_rd0", "mcasp1_ahclkx", |
| 274 |
"mcasp1_ahclkr", "mcasp1_aclkr", "mcasp0_axr3", NULL),
|
|
| 276 |
"mcasp1_ahclkr", "mcasp1_aclkr", "mcasp0_axr3", "gpio2_21"),
|
|
| 275 | 277 |
_AM33XX_MUXENTRY(MII1_REFCLK, 0, |
| 276 | 278 |
"rmii1_refclk", NULL, "spi1_cs0", NULL, |
| 277 | 279 |
"mcasp1_axr3", "mmc0_pow", "mcasp1_ahclkx", "gpio0_29"), |
| 278 | 280 |
_AM33XX_MUXENTRY(MDIO_DATA, 0, |
| 279 | 281 |
"mdio_data", NULL, NULL, NULL, |
| 280 |
"mmc0_sdcd", "mmc1_cmd", "mmc2_cmd", NULL),
|
|
| 282 |
"mmc0_sdcd", "mmc1_cmd", "mmc2_cmd", "gpio0_0"),
|
|
| 281 | 283 |
_AM33XX_MUXENTRY(MDIO_CLK, 0, |
| 282 | 284 |
"mdio_clk", NULL, NULL, NULL, |
| 283 |
"mmc0_sdwp", "mmc1_clk", "mmc2_clk", NULL),
|
|
| 285 |
"mmc0_sdwp", "mmc1_clk", "mmc2_clk", "gpio0_1"),
|
|
| 284 | 286 |
_AM33XX_MUXENTRY(SPI0_SCLK, 0, |
| 285 |
"spi0_sclk", "uart2_rxd", NULL, NULL,
|
|
| 287 |
"spi0_sclk", "uart2_rxd", "i2c2_sda", NULL,
|
|
| 286 | 288 |
NULL, NULL, NULL, "gpio0_2"), |
| 287 | 289 |
_AM33XX_MUXENTRY(SPI0_D0, 0, |
| 288 |
"spi0_d0", "uart2_txd", NULL, NULL,
|
|
| 290 |
"spi0_d0", "uart2_txd", "i2c2_scl", NULL,
|
|
| 289 | 291 |
NULL, NULL, NULL, "gpio0_3"), |
| 290 | 292 |
_AM33XX_MUXENTRY(SPI0_D1, 0, |
| 291 | 293 |
"spi0_d1", "mmc1_sdwp", "i2c1_sda", NULL, |
| ... | ... | |
| 306 | 308 |
"uart0_rtsn", "uart4_txd", "d_can1_rx", "i2c1_scl", |
| 307 | 309 |
"spi1_d1", "spi1_cs0", "pr1_edc_sync1_out", "gpio1_9"), |
| 308 | 310 |
_AM33XX_MUXENTRY(UART0_RXD, 0, |
| 309 |
"uart0_rxd", "spi1_cs0", "d_can0_tx", NULL,
|
|
| 310 |
NULL, NULL, NULL, NULL),
|
|
| 311 |
"uart0_rxd", "spi1_cs0", "d_can0_tx", "i2c2_sda",
|
|
| 312 |
NULL, NULL, NULL, "gpio1_10"),
|
|
| 311 | 313 |
_AM33XX_MUXENTRY(UART0_TXD, 0, |
| 312 |
"uart0_txd", "spi1_cs1", "d_can0_rx", NULL,
|
|
| 313 |
NULL, NULL, NULL, NULL),
|
|
| 314 |
"uart0_txd", "spi1_cs1", "d_can0_rx", "i2c2_scl",
|
|
| 315 |
NULL, NULL, NULL, "gpio1_11"),
|
|
| 314 | 316 |
_AM33XX_MUXENTRY(UART1_CTSN, 0, |
| 315 | 317 |
"uart1_ctsn", NULL, NULL, "i2c2_sda", |
| 316 |
"spi1_cs0", NULL, NULL, NULL),
|
|
| 318 |
"spi1_cs0", NULL, NULL, "gpio0_12"),
|
|
| 317 | 319 |
_AM33XX_MUXENTRY(UART1_RTSN, 0, |
| 318 | 320 |
"uart1_rtsn", NULL, NULL, "i2c2_scl", |
| 319 |
"spi1_cs1", NULL, NULL, NULL),
|
|
| 321 |
"spi1_cs1", NULL, NULL, "gpio0_13"),
|
|
| 320 | 322 |
_AM33XX_MUXENTRY(UART1_RXD, 0, |
| 321 |
"uart1_rxd", "mmc1_sdwp", "d_can1_tx", NULL,
|
|
| 323 |
"uart1_rxd", "mmc1_sdwp", "d_can1_tx", "i2c1_sda",
|
|
| 322 | 324 |
NULL, "pr1_uart0_rxd_mux1", NULL, "gpio0_14"), |
| 323 | 325 |
_AM33XX_MUXENTRY(UART1_TXD, 0, |
| 324 |
"uart1_txd", "mmc2_sdwp", "d_can1_rx", NULL,
|
|
| 326 |
"uart1_txd", "mmc2_sdwp", "d_can1_rx", "i2c1_scl",
|
|
| 325 | 327 |
NULL, "pr1_uart0_txd_mux1", NULL, "gpio0_15"), |
| 326 | 328 |
_AM33XX_MUXENTRY(I2C0_SDA, 0, |
| 327 | 329 |
"i2c0_sda", NULL, NULL, NULL, |
| ... | ... | |
| 331 | 333 |
NULL, NULL, NULL, "gpio3_6"), |
| 332 | 334 |
_AM33XX_MUXENTRY(MCASP0_ACLKX, 0, |
| 333 | 335 |
"mcasp0_aclkx", "ehrpwm0a", NULL, "spi1_sclk", |
| 334 |
"mmc0_sdcd", "pr1_pru0_pru_r30_0", "pr1_pru0_pru_r31_0", |
|
| 335 |
"gpio3_14"), |
|
| 336 |
"mmc0_sdcd", "pr1_pru0_pru_r30_0", "pr1_pru0_pru_r31_0", "gpio3_14"), |
|
| 336 | 337 |
_AM33XX_MUXENTRY(MCASP0_FSX, 0, |
| 337 | 338 |
"mcasp0_fsx", NULL, NULL, "spi1_d0", |
| 338 |
"mmc1_sdcd", NULL, NULL, NULL),
|
|
| 339 |
"mmc1_sdcd", NULL, NULL, "gpio3_15"),
|
|
| 339 | 340 |
_AM33XX_MUXENTRY(MCASP0_AXR0, 0, |
| 340 | 341 |
"mcasp0_axr0", NULL, NULL, "spi1_d1", |
| 341 |
"mmc2_sdcd", NULL, NULL, NULL),
|
|
| 342 |
"mmc2_sdcd", NULL, NULL, "gpio3_16"),
|
|
| 342 | 343 |
_AM33XX_MUXENTRY(MCASP0_AHCLKR, 0, |
| 343 | 344 |
"mcasp0_ahclkr", NULL, "mcasp0_axr2", "spi1_cs0", |
| 344 | 345 |
NULL, NULL, NULL, "gpio3_17"), |
| ... | ... | |
| 352 | 353 |
"mcasp0_axr1", NULL, NULL, "mcasp1_axr0", |
| 353 | 354 |
NULL, NULL, NULL, "gpio3_20"), |
| 354 | 355 |
_AM33XX_MUXENTRY(MCASP0_AHCLKX, 0, |
| 355 |
"mcasp0_ahclkx", "mcasp0_axr3", NULL, "mcasp1_axr1",
|
|
| 356 |
"mcasp0_ahclkx", NULL, "mcasp0_axr3", "mcasp1_axr1",
|
|
| 356 | 357 |
NULL, NULL, NULL, "gpio3_21"), |
| 357 | 358 |
_AM33XX_MUXENTRY(XDMA_EVENT_INTR0, 0, |
| 358 | 359 |
"xdma_event_intr0", NULL, NULL, NULL, |
| ... | ... | |
| 392 | 393 |
NULL, NULL, NULL, NULL), |
| 393 | 394 |
_AM33XX_MUXENTRY(EMU0, 0, |
| 394 | 395 |
NULL, NULL, NULL, NULL, |
| 395 |
NULL, NULL, NULL, NULL),
|
|
| 396 |
NULL, NULL, NULL, "gpio3_7"),
|
|
| 396 | 397 |
_AM33XX_MUXENTRY(EMU1, 0, |
| 397 | 398 |
NULL, NULL, NULL, NULL, |
| 398 |
NULL, NULL, NULL, NULL),
|
|
| 399 |
NULL, NULL, NULL, "gpio3_8"),
|
|
| 399 | 400 |
_AM33XX_MUXENTRY(RTC_XTALIN, 0, |
| 400 | 401 |
NULL, NULL, NULL, NULL, |
| 401 | 402 |
NULL, NULL, NULL, NULL), |
| ... | ... | |
| 618 | 619 |
return 0; |
| 619 | 620 |
} |
| 620 | 621 |
#endif |
| 622 |
|
|
| drivers/net/cpsw.c | ||
|---|---|---|
| 441 | 441 |
mac_control |= BIT(15); |
| 442 | 442 |
if (phy->duplex) |
| 443 | 443 |
mac_control |= BIT(0); /* FULLDUPLEXEN */ |
| 444 |
if (phy->interface == PHY_INTERFACE_MODE_RGMII) /* RGMII */
|
|
| 444 |
if (phy->interface == PHY_INTERFACE_MODE_RMII) /* RMII */
|
|
| 445 | 445 |
mac_control |= (BIT(15)|BIT(16)); |
| 446 | 446 |
*link = true; |
| 447 | 447 |
} else {
|
| ... | ... | |
| 450 | 450 |
mac_control = 0; |
| 451 | 451 |
} |
| 452 | 452 | |
| 453 |
// printk("danm 2 - mac control 0x%x 0x%p slave num %x, slave port 0x%x\n",mac_control,
|
|
| 454 |
// danm &slave->sliver->mac_control,slave->slave_num,slave_port); |
|
| 455 | ||
| 453 | 456 |
if (mac_control != slave->mac_control) {
|
| 454 | 457 |
phy_print_status(phy); |
| 455 | 458 |
__raw_writel(mac_control, &slave->sliver->mac_control); |
| ... | ... | |
| 564 | 567 |
return; |
| 565 | 568 | |
| 566 | 569 |
phy_addr = phy->addr; |
| 570 |
phy->interface = PHY_INTERFACE_MODE_RMII; |
|
| 567 | 571 | |
| 568 | 572 |
/* Disable 1 Gig mode support if it is not supported */ |
| 569 | 573 |
if (!pdata->gigabit_en) |
