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RE: Ethernet RMII2 working in u-boot, but not kernel ยป skyline-0002-sent-to-criticallink-for-review.patch

dan mcgee, 10/24/2013 01:14 PM

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arch/arm/mach-omap2/baseboard-mityarm335x-devkit.c
*
*****************************************************************************/
static struct pinmux_config rmii2_pin_mux[] = {
{"gpmc_csn3.rmii2_crs_dv", AM33XX_PIN_INPUT_PULLUP},
// {"gpmc_wait0.rmii2_crs_dv", AM33XX_PIN_INPUT_PULLUP},
{"gpmc_a0.rmii2_txen", AM33XX_PIN_OUTPUT}, // --
{"gpmc_a5.rmii2_txd0", AM33XX_PIN_OUTPUT}, // --
{"gpmc_a4.rmii2_txd1", AM33XX_PIN_OUTPUT}, // ---
{"gpmc_a11.rmii2_rxd0", AM33XX_PIN_INPUT_PULLDOWN}, // --
{"gpmc_a10.rmii2_rxd1", AM33XX_PIN_INPUT_PULLDOWN}, // --
{"mii1_col.rmii2_refclk", AM33XX_PIN_INPUT_PULLDOWN}, // --
{"mdio_data.mdio_data", AM33XX_PIN_INPUT_PULLUP},
{"mdio_clk.mdio_clk", AM33XX_PIN_OUTPUT_PULLUP},
{NULL, 0}
};
static struct pinmux_config rgmii2_pin_mux[] = {
{"gpmc_a0.rgmii2_tctl", AM33XX_PIN_OUTPUT},
{"gpmc_a1.rgmii2_rctl", AM33XX_PIN_INPUT_PULLDOWN},
......
};
static struct pinmux_config lcdc_pin_mux[] = {
#if 0 //danm
{"lcd_data0.lcd_data0", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
{"lcd_data1.lcd_data1", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
{"lcd_data2.lcd_data2", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA},
......
{"lcd_ac_bias_en.lcd_ac_bias_en", AM33XX_PIN_OUTPUT},
/* GPIO for the backlight */
{ "mcasp0_aclkx.gpio3_14", AM33XX_PIN_OUTPUT},
#endif
{NULL, 0}
};
......
{"mmc0_dat0.mmc0_dat0", AM33XX_PIN_INPUT_PULLUP},
{"mmc0_clk.mmc0_clk", AM33XX_PIN_INPUT_PULLUP},
{"mmc0_cmd.mmc0_cmd", AM33XX_PIN_INPUT_PULLUP},
{"mii1_txen.gpio3_3", AM33XX_PIN_INPUT_PULLUP}, /* SD Card Detect */
{"mii1_col.gpio3_0", AM33XX_PIN_INPUT_PULLUP}, /* SD Write Protect */
// danm {"mii1_txen.gpio3_3", AM33XX_PIN_INPUT_PULLUP}, /* SD Card Detect */
// {"mii1_col.gpio3_0", AM33XX_PIN_INPUT_PULLUP}, /* SD Write Protect */
{NULL, 0}
};
......
};
static struct pinmux_config expansion_pin_mux[] = {
{"uart0_ctsn.uart4_rxd", AM33XX_PIN_INPUT_PULLUP},/* Exp0 RX */
{"uart0_rtsn.uart4_txd", AM33XX_PULL_ENBL}, /* Exp0 TX */
{"mii1_rxd3.uart3_rxd", AM33XX_PIN_INPUT_PULLUP},/* Exp1 RX */
{"mii1_rxd2.uart3_txd", AM33XX_PULL_ENBL}, /* Exp1 TX */
{"mii1_rxd1.gpio2_20", AM33XX_PULL_ENBL}, /* Exp1 TX EN */
{"mii1_txclk.gpio3_9", AM33XX_PULL_ENBL}, /* Exp0 TX EN */
{"uart1_rxd.uart1_rxd", AM33XX_PIN_INPUT_PULLUP},/* Exp0 RX */
{"uart1_txd.uart1_txd", AM33XX_PULL_ENBL}, /* Exp0 TX */
{"mii1_rxd3.uart1_dtrn", AM33XX_PULL_ENBL}, /* uart 1 modem */
{"mii1_rxclk..uart1_dsrn", AM33XX_PULL_ENBL}, /* */
{"mii1_txclk.uart1_dcdn", AM33XX_PULL_ENBL}, /* */
{"spi0_sclk.uart2_rxd", AM33XX_PIN_INPUT_PULLUP},/* Exp0 RX */
{"spi0_d0.uart2_txd", AM33XX_PULL_ENBL}, /* Exp0 TX */
{"spi0_cs1.uart3_rxd", AM33XX_PIN_INPUT_PULLUP},/*- Exp0 RX */
{"mii1_rxd2.uart3_txd", AM33XX_PULL_ENBL}, /* - Exp0 TX */
{"mii1_txd3.uart4_rxd", AM33XX_PIN_INPUT_PULLUP},/* - Exp0 RX */
{"mii1_txd2.uart4_txd", AM33XX_PULL_ENBL}, /* Exp0 TX */
{"lcd_data9.uart5_rxd", AM33XX_PIN_INPUT_PULLUP},/*- Exp0 RX */
{"lcd_data8.uart5_txd", AM33XX_PULL_ENBL}, /*- Exp0 TX */
{NULL, 0}
};
static struct pinmux_config usb_pin_mux[] = {
{"usb0_drvvbus.usb0_drvvbus", AM33XX_PIN_OUTPUT},
{"usb1_drvvbus.usb1_drvvbus", AM33XX_PIN_OUTPUT},
......
{
.mmc = 1,
.caps = MMC_CAP_4_BIT_DATA,
.gpio_cd = GPIO_TO_PIN(3, 3),
.gpio_wp = GPIO_TO_PIN(3, 0),
.gpio_cd = -EINVAL, // GPIO_TO_PIN(3, 3),
.gpio_wp = -EINVAL, //GPIO_TO_PIN(3, 0),
.ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
},
{
......
static __init void baseboard_setup_enet(void)
{
/* pinmux */
setup_pin_mux(rgmii2_pin_mux);
setup_pin_mux(rmii2_pin_mux);
/* network configuration done in SOM code */
/* PHY address setup? */
arch/arm/mach-omap2/board-mityarm335x.c
am33xx_mux_init(NULL);
omap_serial_init();
am335x_rtc_init();
am33xx_cpsw_init(1); /* 1 == enable gigabit */
am33xx_cpsw_init(0); /* 1 == enable gigabit */
mityarm335x_i2c_init();
omap_sdrc_init(NULL, NULL);
spi1_init();
arch/arm/mach-omap2/devices.c
#ifdef CONFIG_BASEBOARD_MITYARM335X_TESTFIXTURE
.phy_id = "0:01",
#else
.phy_id = "0:00",
.phy_id = "0:01",
#endif
},
......
#ifdef CONFIG_BASEBOARD_MITYARM335X_TESTFIXTURE
.phy_id = "0:00",
#else
.phy_id = "0:01",
.phy_id = "0:00",
#endif
},
};
......
.bd_ram_size = SZ_16K,
.rx_descs = 64,
.mac_control = BIT(5), /* MIIEN */
.gigabit_en = 1,
.gigabit_en = 0,
.host_port_num = 0,
.no_bd_ram = false,
.version = CPSW_VERSION_2,
......
am33xx_cpsw_pdata.gigabit_en = gigen;
memcpy(am33xx_cpsw_pdata.mac_addr,
am33xx_cpsw_slaves[0].mac_addr, ETH_ALEN);
platform_device_register(&am33xx_cpsw_mdiodevice);
platform_device_register(&am33xx_cpsw_device);
#define MII_MODE_ENABLE 0x0
#define RMII_MODE_ENABLE 0x4 //5
#define RGMII_MODE_ENABLE 0xA
#define MAC_MII_SEL 0x650
#define SMA2_ADDR 0x1320
__raw_writel(RMII_MODE_ENABLE | 0xb0, //danm
AM33XX_CTRL_REGADDR(MAC_MII_SEL));
__raw_writel(0x0, //danm
AM33XX_CTRL_REGADDR(SMA2_ADDR));
printk("%s gmii_sel 0x%x\n",__func__,
__raw_readl(AM33XX_CTRL_REGADDR(MAC_MII_SEL))); //danm
clk_add_alias(NULL, dev_name(&am33xx_cpsw_mdiodevice.dev),
NULL, &am33xx_cpsw_device.dev);
}
arch/arm/mach-omap2/mux33xx.c
/*
* AM33XX mux data
*
......
static struct omap_mux __initdata am33xx_muxmodes[] = {
_AM33XX_MUXENTRY(GPMC_AD0, 0,
"gpmc_ad0", "mmc1_dat0", NULL, NULL,
NULL, NULL, NULL, NULL),
NULL, NULL, NULL, "gpio1_0"), // danm
_AM33XX_MUXENTRY(GPMC_AD1, 0,
"gpmc_ad1", "mmc1_dat1", NULL, NULL,
NULL, NULL, NULL, NULL),
NULL, NULL, NULL, "gpio1_1"),
_AM33XX_MUXENTRY(GPMC_AD2, 0,
"gpmc_ad2", "mmc1_dat2", NULL, NULL,
NULL, NULL, NULL, NULL),
NULL, NULL, NULL, "gpio1_2"),
_AM33XX_MUXENTRY(GPMC_AD3, 0,
"gpmc_ad3", "mmc1_dat3", NULL, NULL,
NULL, NULL, NULL, NULL),
NULL, NULL, NULL, "gpio1_3"),
_AM33XX_MUXENTRY(GPMC_AD4, 0,
"gpmc_ad4", "mmc1_dat4", NULL, NULL,
NULL, NULL, NULL, NULL),
NULL, NULL, NULL, "gpio1_4"),
_AM33XX_MUXENTRY(GPMC_AD5, 0,
"gpmc_ad5", "mmc1_dat5", NULL, NULL,
NULL, NULL, NULL, NULL),
NULL, NULL, NULL, "gpio1_5"),
_AM33XX_MUXENTRY(GPMC_AD6, 0,
"gpmc_ad6", "mmc1_dat6", NULL, NULL,
NULL, NULL, NULL, NULL),
NULL, NULL, NULL, "gpio1_6"),
_AM33XX_MUXENTRY(GPMC_AD7, 0,
"gpmc_ad7", "mmc1_dat7", NULL, NULL,
NULL, NULL, NULL, NULL),
NULL, NULL, NULL, "gpio1_7"),
_AM33XX_MUXENTRY(GPMC_AD8, 0,
"gpmc_ad8", "lcd_data16", "mmc1_dat0", "mmc2_dat4",
NULL, NULL, NULL, "gpio0_22"),
_AM33XX_MUXENTRY(GPMC_AD9, 0,
"gpmc_ad9", "lcd_data17", "mmc1_dat1", "mmc2_dat5",
NULL, NULL, NULL, "gpio0_23"),
"ehrpwm2B", NULL, NULL, "gpio0_23"),
_AM33XX_MUXENTRY(GPMC_AD10, 0,
"gpmc_ad10", "lcd_data18", "mmc1_dat2", "mmc2_dat6",
NULL, NULL, NULL, "gpio0_26"),
......
NULL, NULL, "mcasp0_axr1", "gpio1_27"),
_AM33XX_MUXENTRY(GPMC_WAIT0, 0,
"gpmc_wait0", "mii2_crs", NULL, "rmii2_crs_dv",
"mmc1_sdcd", NULL, NULL, NULL),
"mmc1_sdcd", NULL, NULL, "gpio0_30"),
_AM33XX_MUXENTRY(GPMC_WPN, 0,
"gpmc_wpn", "mii2_rxerr", NULL, "rmii2_rxerr",
"mmc2_sdcd", NULL, NULL, NULL),
"mmc2_sdcd", NULL, NULL, "gpio0_31"),
_AM33XX_MUXENTRY(GPMC_BEN1, 0,
"gpmc_ben1", "mii2_col", NULL, "mmc2_dat3",
NULL, NULL, "mcasp0_aclkr", "gpio1_28"),
_AM33XX_MUXENTRY(GPMC_CSN0, 0,
"gpmc_csn0", NULL, NULL, NULL,
NULL, NULL, NULL, "mmc1_sdwp"),
NULL, NULL, NULL, "gpio1_29"),
_AM33XX_MUXENTRY(GPMC_CSN1, 0,
"gpmc_csn1", NULL, "mmc1_clk", NULL,
NULL, NULL, NULL, "gpio1_30"),
......
"gpmc_csn2", NULL, "mmc1_cmd", NULL,
NULL, NULL, NULL, "gpio1_31"),
_AM33XX_MUXENTRY(GPMC_CSN3, 0,
"gpmc_csn3", NULL, NULL, "mmc2_cmd",
"gpmc_csn3", NULL, "rmii2_crs_dv", "mmc2_cmd",
NULL, NULL, NULL, "gpio2_0"),
_AM33XX_MUXENTRY(GPMC_CLK, 0,
"gpmc_clk", "lcd_memory_clk_mux", NULL, "mmc2_clk",
......
NULL, NULL, NULL, "mmc1_sdcd"),
_AM33XX_MUXENTRY(GPMC_OEN_REN, 0,
"gpmc_oen_ren", NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
NULL, NULL, NULL, "gpio2_3"),
_AM33XX_MUXENTRY(GPMC_WEN, 0,
"gpmc_wen", NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
NULL, NULL, NULL, "gpio2_4"),
_AM33XX_MUXENTRY(GPMC_BEN0_CLE, 0,
"gpmc_ben0_cle", NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
NULL, NULL, NULL, "gpio2_5"),
_AM33XX_MUXENTRY(LCD_DATA0, 0,
"lcd_data0", "gpmc_a0", NULL, NULL,
NULL, NULL, NULL, "gpio2_6"),
......
NULL, NULL, NULL, "gpio2_13"),
_AM33XX_MUXENTRY(LCD_DATA8, 0,
"lcd_data8", "gpmc_a12", NULL, "mcasp0_aclkx",
NULL, NULL, "uart2_ctsn", "gpio2_14"),
"uart5_txd", NULL, "uart2_ctsn", "gpio2_14"),
_AM33XX_MUXENTRY(LCD_DATA9, 0,
"lcd_data9", "gpmc_a13", NULL, "mcasp0_fsx",
NULL, NULL, "uart2_rtsn", "gpio2_15"),
"uart5_rxd", NULL, "uart2_rtsn", "gpio2_15"),
_AM33XX_MUXENTRY(LCD_DATA10, 0,
"lcd_data10", "gpmc_a14", NULL, "mcasp0_axr0",
NULL, NULL, NULL, "gpio2_16"),
......
_AM33XX_MUXENTRY(MMC0_DAT0, 0,
"mmc0_dat0", NULL, NULL, NULL,
NULL, NULL, NULL, "gpio2_29"),
_AM33XX_MUXENTRY(MMC0_CLK, 0,
"mmc0_clk", NULL, NULL, NULL,
_AM33XX_MUXENTRY(MMC0_CLK, 0, // skyline danm
"mmc0_clk", "gpmc_a24", "uart3_ctsn", "uart2_rxd",
NULL, NULL, NULL, "gpio2_30"),
_AM33XX_MUXENTRY(MMC0_CMD, 0,
"mmc0_cmd", NULL, NULL, NULL,
_AM33XX_MUXENTRY(MMC0_CMD, 0, // skyline danm
"mmc0_cmd", "gpmc_a25", "uart3_rtsn", "uart2_txd",
NULL, NULL, NULL, "gpio2_31"),
_AM33XX_MUXENTRY(MII1_COL, 0,
"mii1_col", "rmii2_refclk", "spi1_sclk", NULL,
"mcasp1_axr2", "mmc2_dat3", "mcasp0_axr2", "gpio3_0"),
_AM33XX_MUXENTRY(MII1_CRS, 0,
"mii1_crs", "rmii1_crs_dv", "spi1_d0", "i2c1_sda",
"mcasp1_aclkx", NULL, NULL, NULL),
"mcasp1_aclkx", NULL, NULL, "gpio3_1"),
_AM33XX_MUXENTRY(MII1_RXERR, 0,
"mii1_rxerr", "rmii1_rxerr", "spi1_d1", "i2c1_scl",
"mcasp1_fsx", NULL, NULL, NULL),
"mcasp1_fsx", NULL, NULL, "gpio3_2"),
_AM33XX_MUXENTRY(MII1_TXEN, 0,
"mii1_txen", "rmii1_txen", "rgmii1_tctl", NULL,
"mcasp1_axr0", NULL, "mmc2_cmd", "gpio3_3"),
_AM33XX_MUXENTRY(MII1_RXDV, 0,
"mii1_rxdv", NULL, "rgmii1_rctl", NULL,
"mcasp1_aclx", "mmc2_dat0", "mcasp0_aclkr", NULL),
"mcasp1_aclx", "mmc2_dat0", "mcasp0_aclkr", "gpio3_4"),
_AM33XX_MUXENTRY(MII1_TXD3, 0,
"mii1_txd3", "d_can0_tx", "rgmii1_td3", NULL,
"mcasp1_fsx", "mmc2_dat1", "mcasp0_fsr", NULL),
"mii1_txd3", "d_can0_tx", "rgmii1_td3", "uart4_rxd",
"mcasp1_fsx", "mmc2_dat1", "mcasp0_fsr", "gpio0_16"),
_AM33XX_MUXENTRY(MII1_TXD2, 0,
"mii1_txd2", "d_can0_rx", "rgmii1_td2", NULL,
"mcasp1_axr0", "mmc2_dat2", "mcasp0_ahclkx", NULL),
"mii1_txd2", "d_can0_rx", "rgmii1_td2", "uart4_txd",
"mcasp1_axr0", "mmc2_dat2", "mcasp0_ahclkx", "gpio0_17"),
_AM33XX_MUXENTRY(MII1_TXD1, 0,
"mii1_txd1", "rmii1_txd1", "rgmii1_td1", "mcasp1_fsr",
"mcasp1_axr1", NULL, "mmc1_cmd", NULL),
"mcasp1_axr1", NULL, "mmc1_cmd", "gpio0_21"),
_AM33XX_MUXENTRY(MII1_TXD0, 0,
"mii1_txd0", "rmii1_txd0", "rgmii1_td0", "mcasp1_axr2",
"mcasp1_aclkr", NULL, "mmc1_clk", "gpio0_28"),
_AM33XX_MUXENTRY(MII1_TXCLK, 0,
"mii1_txclk", NULL, "rgmii1_tclk", "mmc0_dat7",
"mmc1_dat0", NULL, "mcasp0_aclkx", "gpio3_9"),
"mmc1_dat0", "uart1_dcdn", "mcasp0_aclkx", "gpio3_9"),
_AM33XX_MUXENTRY(MII1_RXCLK, 0,
"mii1_rxclk", NULL, "rgmii1_rclk", "mmc0_dat6",
"mmc1_dat1", NULL, "mcasp0_fsx", NULL),
"mmc1_dat1", "uart1_dsrn", "mcasp0_fsx", "gpio3_10"),
_AM33XX_MUXENTRY(MII1_RXD3, 0,
"mii1_rxd3", "uart3_rxd", "rgmii1_rd3", "mmc0_dat5",
"mmc1_dat2", "uart1_dtrn", "mcasp0_axr0", "gpio2_18"),
......
"mcasp1_fsr", NULL, "mmc2_clk", "gpio2_20"),
_AM33XX_MUXENTRY(MII1_RXD0, 0,
"mii1_rxd0", "rmii1_rxd0", "rgmii1_rd0", "mcasp1_ahclkx",
"mcasp1_ahclkr", "mcasp1_aclkr", "mcasp0_axr3", NULL),
"mcasp1_ahclkr", "mcasp1_aclkr", "mcasp0_axr3", "gpio2_21"),
_AM33XX_MUXENTRY(MII1_REFCLK, 0,
"rmii1_refclk", NULL, "spi1_cs0", NULL,
"mcasp1_axr3", "mmc0_pow", "mcasp1_ahclkx", "gpio0_29"),
_AM33XX_MUXENTRY(MDIO_DATA, 0,
"mdio_data", NULL, NULL, NULL,
"mmc0_sdcd", "mmc1_cmd", "mmc2_cmd", NULL),
"mmc0_sdcd", "mmc1_cmd", "mmc2_cmd", "gpio0_0"),
_AM33XX_MUXENTRY(MDIO_CLK, 0,
"mdio_clk", NULL, NULL, NULL,
"mmc0_sdwp", "mmc1_clk", "mmc2_clk", NULL),
"mmc0_sdwp", "mmc1_clk", "mmc2_clk", "gpio0_1"),
_AM33XX_MUXENTRY(SPI0_SCLK, 0,
"spi0_sclk", "uart2_rxd", NULL, NULL,
"spi0_sclk", "uart2_rxd", "i2c2_sda", NULL,
NULL, NULL, NULL, "gpio0_2"),
_AM33XX_MUXENTRY(SPI0_D0, 0,
"spi0_d0", "uart2_txd", NULL, NULL,
"spi0_d0", "uart2_txd", "i2c2_scl", NULL,
NULL, NULL, NULL, "gpio0_3"),
_AM33XX_MUXENTRY(SPI0_D1, 0,
"spi0_d1", "mmc1_sdwp", "i2c1_sda", NULL,
......
"uart0_rtsn", "uart4_txd", "d_can1_rx", "i2c1_scl",
"spi1_d1", "spi1_cs0", "pr1_edc_sync1_out", "gpio1_9"),
_AM33XX_MUXENTRY(UART0_RXD, 0,
"uart0_rxd", "spi1_cs0", "d_can0_tx", NULL,
NULL, NULL, NULL, NULL),
"uart0_rxd", "spi1_cs0", "d_can0_tx", "i2c2_sda",
NULL, NULL, NULL, "gpio1_10"),
_AM33XX_MUXENTRY(UART0_TXD, 0,
"uart0_txd", "spi1_cs1", "d_can0_rx", NULL,
NULL, NULL, NULL, NULL),
"uart0_txd", "spi1_cs1", "d_can0_rx", "i2c2_scl",
NULL, NULL, NULL, "gpio1_11"),
_AM33XX_MUXENTRY(UART1_CTSN, 0,
"uart1_ctsn", NULL, NULL, "i2c2_sda",
"spi1_cs0", NULL, NULL, NULL),
"spi1_cs0", NULL, NULL, "gpio0_12"),
_AM33XX_MUXENTRY(UART1_RTSN, 0,
"uart1_rtsn", NULL, NULL, "i2c2_scl",
"spi1_cs1", NULL, NULL, NULL),
"spi1_cs1", NULL, NULL, "gpio0_13"),
_AM33XX_MUXENTRY(UART1_RXD, 0,
"uart1_rxd", "mmc1_sdwp", "d_can1_tx", NULL,
"uart1_rxd", "mmc1_sdwp", "d_can1_tx", "i2c1_sda",
NULL, "pr1_uart0_rxd_mux1", NULL, "gpio0_14"),
_AM33XX_MUXENTRY(UART1_TXD, 0,
"uart1_txd", "mmc2_sdwp", "d_can1_rx", NULL,
"uart1_txd", "mmc2_sdwp", "d_can1_rx", "i2c1_scl",
NULL, "pr1_uart0_txd_mux1", NULL, "gpio0_15"),
_AM33XX_MUXENTRY(I2C0_SDA, 0,
"i2c0_sda", NULL, NULL, NULL,
......
NULL, NULL, NULL, "gpio3_6"),
_AM33XX_MUXENTRY(MCASP0_ACLKX, 0,
"mcasp0_aclkx", "ehrpwm0a", NULL, "spi1_sclk",
"mmc0_sdcd", "pr1_pru0_pru_r30_0", "pr1_pru0_pru_r31_0",
"gpio3_14"),
"mmc0_sdcd", "pr1_pru0_pru_r30_0", "pr1_pru0_pru_r31_0", "gpio3_14"),
_AM33XX_MUXENTRY(MCASP0_FSX, 0,
"mcasp0_fsx", NULL, NULL, "spi1_d0",
"mmc1_sdcd", NULL, NULL, NULL),
"mmc1_sdcd", NULL, NULL, "gpio3_15"),
_AM33XX_MUXENTRY(MCASP0_AXR0, 0,
"mcasp0_axr0", NULL, NULL, "spi1_d1",
"mmc2_sdcd", NULL, NULL, NULL),
"mmc2_sdcd", NULL, NULL, "gpio3_16"),
_AM33XX_MUXENTRY(MCASP0_AHCLKR, 0,
"mcasp0_ahclkr", NULL, "mcasp0_axr2", "spi1_cs0",
NULL, NULL, NULL, "gpio3_17"),
......
"mcasp0_axr1", NULL, NULL, "mcasp1_axr0",
NULL, NULL, NULL, "gpio3_20"),
_AM33XX_MUXENTRY(MCASP0_AHCLKX, 0,
"mcasp0_ahclkx", "mcasp0_axr3", NULL, "mcasp1_axr1",
"mcasp0_ahclkx", NULL, "mcasp0_axr3", "mcasp1_axr1",
NULL, NULL, NULL, "gpio3_21"),
_AM33XX_MUXENTRY(XDMA_EVENT_INTR0, 0,
"xdma_event_intr0", NULL, NULL, NULL,
......
NULL, NULL, NULL, NULL),
_AM33XX_MUXENTRY(EMU0, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
NULL, NULL, NULL, "gpio3_7"),
_AM33XX_MUXENTRY(EMU1, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
NULL, NULL, NULL, "gpio3_8"),
_AM33XX_MUXENTRY(RTC_XTALIN, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
......
return 0;
}
#endif
drivers/net/cpsw.c
mac_control |= BIT(15);
if (phy->duplex)
mac_control |= BIT(0); /* FULLDUPLEXEN */
if (phy->interface == PHY_INTERFACE_MODE_RGMII) /* RGMII */
if (phy->interface == PHY_INTERFACE_MODE_RMII) /* RMII */
mac_control |= (BIT(15)|BIT(16));
*link = true;
} else {
......
mac_control = 0;
}
// printk("danm 2 - mac control 0x%x 0x%p slave num %x, slave port 0x%x\n",mac_control,
// danm &slave->sliver->mac_control,slave->slave_num,slave_port);
if (mac_control != slave->mac_control) {
phy_print_status(phy);
__raw_writel(mac_control, &slave->sliver->mac_control);
......
return;
phy_addr = phy->addr;
phy->interface = PHY_INTERFACE_MODE_RMII;
/* Disable 1 Gig mode support if it is not supported */
if (!pdata->gigabit_en)
    (1-1/1)
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