| Device Utilization Summary | [-] |
| Slice Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Registers |
1,139 |
18,224 |
6% |
|
| Number used as Flip Flops |
1,139 |
|
|
|
| Number used as Latches |
0 |
|
|
|
| Number used as Latch-thrus |
0 |
|
|
|
| Number used as AND/OR logics |
0 |
|
|
|
| Number of Slice LUTs |
909 |
9,112 |
9% |
|
| Number used as logic |
854 |
9,112 |
9% |
|
| Number using O6 output only |
605 |
|
|
|
| Number using O5 output only |
22 |
|
|
|
| Number using O5 and O6 |
227 |
|
|
|
| Number used as ROM |
0 |
|
|
|
| Number used as Memory |
11 |
2,176 |
1% |
|
| Number used as Dual Port RAM |
0 |
|
|
|
| Number used as Single Port RAM |
8 |
|
|
|
| Number using O6 output only |
0 |
|
|
|
| Number using O5 output only |
0 |
|
|
|
| Number using O5 and O6 |
8 |
|
|
|
| Number used as Shift Register |
3 |
|
|
|
| Number using O6 output only |
3 |
|
|
|
| Number using O5 output only |
0 |
|
|
|
| Number using O5 and O6 |
0 |
|
|
|
| Number used exclusively as route-thrus |
44 |
|
|
|
| Number with same-slice register load |
42 |
|
|
|
| Number with same-slice carry load |
2 |
|
|
|
| Number with other load |
0 |
|
|
|
| Number of occupied Slices |
456 |
2,278 |
20% |
|
| Number of MUXCYs used |
148 |
4,556 |
3% |
|
| Number of LUT Flip Flop pairs used |
1,361 |
|
|
|
| Number with an unused Flip Flop |
353 |
1,361 |
25% |
|
| Number with an unused LUT |
452 |
1,361 |
33% |
|
| Number of fully used LUT-FF pairs |
556 |
1,361 |
40% |
|
| Number of unique control sets |
90 |
|
|
|
Number of slice register sites lost
to control set restrictions |
354 |
18,224 |
1% |
|
| Number of bonded IOBs |
145 |
232 |
62% |
|
| Number of LOCed IOBs |
145 |
145 |
100% |
|
| IOB Flip Flops |
11 |
|
|
|
| Number of RAMB16BWERs |
6 |
32 |
18% |
|
| Number of RAMB8BWERs |
0 |
64 |
0% |
|
| Number of BUFIO2/BUFIO2_2CLKs |
1 |
32 |
3% |
|
| Number used as BUFIO2s |
1 |
|
|
|
| Number used as BUFIO2_2CLKs |
0 |
|
|
|
| Number of BUFIO2FB/BUFIO2FB_2CLKs |
1 |
32 |
3% |
|
| Number used as BUFIO2FBs |
1 |
|
|
|
| Number used as BUFIO2FB_2CLKs |
0 |
|
|
|
| Number of BUFG/BUFGMUXs |
5 |
16 |
31% |
|
| Number used as BUFGs |
5 |
|
|
|
| Number used as BUFGMUX |
0 |
|
|
|
| Number of DCM/DCM_CLKGENs |
1 |
4 |
25% |
|
| Number used as DCMs |
1 |
|
|
|
| Number used as DCM_CLKGENs |
0 |
|
|
|
| Number of ILOGIC2/ISERDES2s |
8 |
248 |
3% |
|
| Number used as ILOGIC2s |
8 |
|
|
|
| Number used as ISERDES2s |
0 |
|
|
|
| Number of IODELAY2/IODRP2/IODRP2_MCBs |
0 |
248 |
0% |
|
| Number of OLOGIC2/OSERDES2s |
3 |
248 |
1% |
|
| Number used as OLOGIC2s |
3 |
|
|
|
| Number used as OSERDES2s |
0 |
|
|
|
| Number of BSCANs |
0 |
4 |
0% |
|
| Number of BUFHs |
0 |
128 |
0% |
|
| Number of BUFPLLs |
0 |
8 |
0% |
|
| Number of BUFPLL_MCBs |
0 |
4 |
0% |
|
| Number of DSP48A1s |
0 |
32 |
0% |
|
| Number of ICAPs |
0 |
1 |
0% |
|
| Number of MCBs |
0 |
2 |
0% |
|
| Number of PCILOGICSEs |
0 |
2 |
0% |
|
| Number of PLL_ADVs |
0 |
2 |
0% |
|
| Number of PMVs |
0 |
1 |
0% |
|
| Number of STARTUPs |
1 |
1 |
100% |
|
| Number of SUSPEND_SYNCs |
0 |
1 |
0% |
|
| Average Fanout of Non-Clock Nets |
3.20 |
|
|
|