# read core version
R 0
R 0
R 0
R 0

# SPI Setup
# Set Divisor (10 MHz), chip select 0
W 9 0005

# Disable delay
W 10 0000
W 10 8008

###########################################################################
# TEST 1
# SPI Mode 0 (CPOL=0, CPHA=0)
# 8-bit transfers, 8 words, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07
#
# Fill FIFO
W 4 0000
w 5 0000
w 4 0001
w 5 0000
w 4 0002
w 5 0000
w 4 0003
w 5 0000
w 4 0004
w 5 0000
w 4 0005
w 5 0000
w 4 0006
w 5 0000
w 4 0007
w 5 0000
# Write control register and go (loopback & dwidth & cpol & cpha & sclk_ctrl & rcv_en;)
W 1 0193
# Wait for transaction to complete
D 2000
# Read back the data
R 4
R 5
R 4 
R 5
R 4
R 5
R 4
R 5
R 4
R 5
R 4
R 5
R 4 
R 5
R 4 
R 5

###########################################################################
# TEST 2
# SPI Mode 1 (CPOL=0, CPHA=1)
# 8-bit transfers, 8 words, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17
#
# Fill FIFO
W 4 0010
w 5 0000
w 4 0011
w 5 0000
w 4 0012
w 5 0000
w 4 0013
w 5 0000
w 4 0014
w 5 0000
w 4 0015
w 5 0000
w 4 0016
w 5 0000
w 4 0017
w 5 0000
# Write control register and go (loopback & dwidth & cpol & cpha & sclk_ctrl & rcv_en;)
W 1 0197
# Wait for transaction to complete
D 2000
# Read back the data
R 4
R 5
R 4 
R 5
R 4
R 5
R 4
R 5
R 4
R 5
R 4
R 5
R 4 
R 5
R 4 
R 5

###########################################################################
# TEST 3
# SPI Mode 2 (CPOL=1, CPHA=0)
# 8-bit transfers, 8 words, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27
#
# Fill FIFO
W 4 0020
w 5 0000
w 4 0021
w 5 0000
w 4 0022
w 5 0000
w 4 0023
w 5 0000
w 4 0024
w 5 0000
w 4 0025
w 5 0000
w 4 0026
w 5 0000
w 4 0027
w 5 0000
# Write control register and go (loopback & dwidth & cpol & cpha & sclk_ctrl & rcv_en;)
W 1 019B
# Wait for transaction to complete
D 2000
# Read back the data
R 4
R 5
R 4 
R 5
R 4
R 5
R 4
R 5
R 4
R 5
R 4
R 5
R 4 
R 5
R 4 
R 5

###########################################################################
# TEST 4
# SPI Mode 3 (CPOL=1, CPHA=1)
# 8-bit transfers, 8 words, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37
#
# Fill FIFO
W 4 0030
w 5 0000
w 4 0031
w 5 0000
w 4 0032
w 5 0000
w 4 0033
w 5 0000
w 4 0034
w 5 0000
w 4 0035
w 5 0000
w 4 0036
w 5 0000
w 4 0037
w 5 0000
# Write control register and go (loopback & dwidth & cpol & cpha & sclk_ctrl & rcv_en;)
W 1 019F
# Wait for transaction to complete
D 2000
# Read back the data
R 4
R 5
R 4 
R 5
R 4
R 5
R 4
R 5
R 4
R 5
R 4
R 5
R 4 
R 5
R 4 
R 5

###########################################################################
# TEST 5
# SPI Mode 0 (CPOL=0, CPHA=0), add delay
# 8-bit transfers, 8 words, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07
#
# Fill FIFO
W 4 00FF
w 5 0000
w 4 00FF
w 5 0000
w 4 00FF
w 5 0000
w 4 00FF
w 5 0000
w 4 00FF
w 5 0000
w 4 00FF
w 5 0000
w 4 00FF
w 5 0000
w 4 00FF
w 5 0000
# Add 8 clock delay register
# Write control register and go (loopback & dwidth & cpol & cpha & sclk_ctrl & rcv_en;)
W 1 0597
# Wait for transaction to complete
D 2000
# Read back the data
R 4
R 5
R 4 
R 5
R 4
R 5
R 4
R 5
R 4
R 5
R 4
R 5
R 4 
R 5
R 4 
R 5