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EMIFA write timing
Added by Steven Hill about 11 years ago
Is there a diagram for the EMIFA write timing like the one in the wiki for read timing? I am having some problems implementing an interface to a THS1206 ADC using RD and WR - for the read, it looks like RD goes high after everything is finished, so it is of no use to me for the THS1206. I would like to know if WR is similar. I have attached the datasheet for the THS1206...
| ths1206.pdf (776 KB) ths1206.pdf |
Replies (3)
RE: EMIFA write timing - Added by Michael Williamson about 11 years ago
Do you mean for the EMIFA from the OMAP-L138 or the signals from the EMIFA_iface.vhd module that CL provides?
I don't have one drawn up, but you do have the source code for the EMIFA_iface.vhd (if that is what you are after) that you could simulate quickly with Xilinx's ISIM or modelsim.
The EMIFA write timings are shown in the OMAP-L138 technical reference manual (see TI's OMAP-L138 webpage). You need to get the proper register settings for the setup, strobe, and hold times, etc. Those are programmable, I can provide them for the ones used by the EMIFA_iface.vhd.
The read strobe is intentionally "late" is it is intended to advance a FIFO. If you need to "pass through" the EMIFA access to an external device via the FPGA I would suggest using a different chip select space and adding the necessary wait states and translation logic in a separate interface module. The EMIFA_iface isn't going to give you enough wait states to have the FPGA act as an intermediate bus interface...
-Mike
RE: EMIFA write timing - Added by Steven Hill about 11 years ago
To read the THS1206 I need two chip selects, which can be the core cs and an address bit. Then I need a read pulse which is enclosed within the chip selects and long enough that the THS1206 has time to drive the data bus so the EMIFA can strobe the data in - what do you think of the idea of using 'oe_n' as that pulse? I'm thinking of modifying the EMIFA module and adding another core output specifically for that read pulse. But I have no idea about unintended consequences...
RE: EMIFA write timing - Added by Michael Williamson about 11 years ago
Hi Steven,
Using a separate chip select (and adjusting the wait timings setup in u-Boot) should make this feasible, but I can't really help much further with a detailed implementation.
If you are not using any of CL's provided cores, you could scrap the EMIFA_iface all together if you are concerned about that.
We could certainly help you with this, if you need it, but I think we'd probably need a small support contract or something.
-Mike
