Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

Hi. Can you give an example of what you are trying to do? Your question
isn't making sense to me.

dabbyeon gamsahabnida. jega halyeoneun il-eun EMIF tongsin-eul jinhaenghalyeogo habnida. FPGA yeje (MDK\examples\industrial_io\fpga\vhdl)eseo IndustrialIO_top yejeleul iyonghago, DSP yeje(MDK\sw\DSP\lib\core\DspFpgaGpio)leul tonghaeseo GPIO yejeleul jinhaeng hayeossseubnida. hyeonjaeneun FPGA yeje(MDK\fpga\vhdl\fifo_dram_sync)tonghae fifo-e jeojangdoen deiteoleul EMIF tongsin-eulo DSPeseo jeonsong bad-eulyeogo hago issseubnida. FPGAeseo fifo_dram_syncleul inseuteonseuhwa hayeo, gijon yeje cheoleom constant CORE_TS_MODULE : integer := 1; constant CORE_I2C_MODULE : integer := 2; constant CORE_LCD_MODULE : integer := 3; constant CORE_DVI_MODULE : integer := 4; constant CORE_GPIO_MODULE : integer := 5; constant CORE_PWM_MODULE : integer := 6; constant CORE_FIFO_MODULE : integer :=7; eseo 7lo dugo EMIF tongsin-eul jinhaenghalyeogo habnida. GPIO silheomsi yejeeseoneun mpGpio = new tcDspFpgaGpio((void*)0x66000280); eulo jusoleul iblyeoghaeseo jinhaenghayeossneunde(jadong-eulo ARMeseo iomapping-eul sikyeojuneungeo gatseubnida.) icheoleom fifo modyulhago tongsin-eul halyeomyeon DSPeseo eotteohge jinhaeng-eul haeya haneunji moleugessseubnida. 0x66000300 jusoleul eotteohge jeog-yong-eul haeyahaneunji moleugessseubnida. ttalo laibeuleoliga issneunji gung-geumhabnida.
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Thank you for answer.

What I'm trying to do is conduct EMIF communication.
We used the IndustrialIO_top example in the FPGA example (MDK\examples\industrial_io\fpga\vhdl) and performed the GPIO example through the DSP example (MDK\sw\DSP\lib\core\DspFpgaGpio). Currently, we are trying to receive data stored in fifo from DSP through EMIF communication through FPGA example (MDK\fpga\vhdl\fifo_dram_sync).
Instantiate fifo_dram_sync in FPGA, like the existing example
constant CORE_TS_MODULE : integer := 1;
constant CORE_I2C_MODULE : integer := 2;
constant CORE_LCD_MODULE : integer := 3;
constant CORE_DVI_MODULE : integer := 4;
constant CORE_GPIO_MODULE : integer := 5;
constant CORE_PWM_MODULE : integer := 6;
constant CORE_FIFO_MODULE : integer :=7;
We are going to set it to 7 and proceed with EMIF communication.

In the GPIO experiment example, mpGpio = new tcDspFpgaGpio((void*)0x66000280); I proceeded by entering the address (I think ARM automatically performs iomapping).

I don't know how to proceed in DSP to communicate with the fifo module like this.
I don't know how to apply the address 0x66000300. I wonder if there is a separate library.

If you have the FPGA portion working by decoding the address to the FIFO using the base_module.vhd file, which generates a read strobe and an enable, etc., then for the DSP all you need to do is create a basic integer pointer and dereference it, for example:

void ReadFromFIFOonDSP(uint16_t* buffer, int len)
{
    uint16_t* ptr = (uint16_t*)0x66000300;
    for (int i = 0; i < len; ++i)
    {
        buffer[i] = *ptr;
    }
}

Thank you for answer.

I'm still a beginner, so my questions may be basic.

If I input o_DBus<= Data in FPGA, will data be transmitted?

As far as I know, EMIF has an address and data, but the example above only has a CS address.

So how should I set the data that matches the address?

I have additional questions.

I would like to perform EMIF communication only with DSP and FPGA, without ARM.

If you proceed without fpga_ctrl.ko, does EMIF communication proceed without ARM?

DSP informed me

void ReadFromFIFOonDSP(uint16_t* buffer, int len) {
uint16_t* ptr = (uint16_t*)0x66000300;
for (int i = 0; i < len; ++i) {
buffer[i] = *ptr;
}
}

Is it possible without performing fpga_ctrl.ko insmod with the above source???

Kyungguk Bok wrote in RE: I have another question regarding EMIF.:

I have additional questions.

I would like to perform EMIF communication only with DSP and FPGA, without ARM.

If you proceed without fpga_ctrl.ko, does EMIF communication proceed without ARM?

As long as your willing to use u-boot on the ARM to load the DSP and the FPGA then I think this should already work. U-boot has to have configured the EMIF to support loading the FPGA.
https://support.criticallink.com/gitweb/?p=u-boot-mitydspl138.git;a=blob;f=board/davinci/mityomapl138/mityomapl138.c;h=9d616ffe99d3f3e4fceae41f90e509b638013d5a;hb=275ff0e76f22e3a47e3cbf72f4aa61083eb507a7#l268