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GPIO toggling/chattering while performing NAND read.

Added by Srinivasa Wunnimani over 4 years ago

Hi,

We have mitySOM board in our product and we are using u-boot-mityarm-335x.tar.gz and building u-boot as below:

/* Export path */
source /opt/criticallink/mitysom-335x_2018-04-16/environment-setup-cortexa8hf-neon-criticallink-linux-gnueabi

/* Build u-boot */
make ARCH=arm CROSS_COMPILE=arm-criticallink-linux-gnueabi- distclean
make CROSS_COMPILE=arm-criticallink-linux-gnueabi- O=srini_mityarm mitysom335x_devkit_256MB_defconfig
make CROSS_COMPILE=arm-criticallink-linux-gnueabi- O=srini_mityarm

We are noticing that GPIO 0_27 (Pin 99 as per MitySOM-335x Processor Card Manual dated 9 February 2018) is being chattering as shown in attached figure. While testing I have made sure that nothing is connected on GPIO 0_27.

This is happening during SPL and also u-boot.

This happens only when it is reading from NAND and it does not happen in SD card boot.

Upon debugging we have found this happens at line 1760 in file drivers/mtd/nand/nand_base.c

1739 read_retry:
1740 if (nand_standard_page_accessors(&chip->ecc))
1741 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1742
1743 /*
1744 * Now read the page into the buffer. Absent an error,
1745 * the read methods return max bitflips per ecc step.
1746 /
1747 if (unlikely(ops->mode == MTD_OPS_RAW))
1748 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1749 oob_required,
1750 page);
1751 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1752 !oob)
1753 ret = chip->ecc.read_subpage(mtd, chip,
1754 col, bytes, bufpoi,
1755 page);
1756 else
1757 {
1758
1759 getc();
1760 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1761 oob_required, page);
1762 getc();
1763 }
1764 if (ret < 0) {
1765 if (use_bufpoi)
1766 / Invalidate page cache */
1767 chip->pagebuf = -1;
1768 break;
1769 }

At any point did you notice such behavior?

I have difficulty in knowing chip->ecc.read_page() calls which function?
Can you please let us know which function is being called by executing line 1760?

Regards
Srinivasa

gpio_0_27_chattering.jpg (3.05 MB) gpio_0_27_chattering.jpg

Replies (36)

RE: GPIO toggling/chattering while performing NAND read. - Added by Srinivasa Wunnimani over 4 years ago

Is boot from nand a requirement to reproduce this?

Yes. GPIO 0_27 (Relay chattering) happens only during NAND boot or any NAND operations.

I would expect it to behave the same when booted from SD card and reading from the NAND using your nand read command.

My expectation was also the same. Just to confirm on this, perform the test with SD boot and NAND read. I am not hearing any sound on relay with this.
i.e) during SD card boot and NAND read command does not toggle the relay.
For this case, I have not captured the waveform on oscilloscope. Same here, due to virus issue I don't have access to oscilloscope.
Once again booted the board with NAND boot and peformed NAND read operation. I am able to hear relay chatting some very clearly.

Hope this test case will help us to corner the problem :)

Regards
Srinivasa

RE: GPIO toggling/chattering while performing NAND read. - Added by Jonathan Cormier over 4 years ago

huh is your sd card MLO and u-boot.img the same one you are programming into nand?

RE: GPIO toggling/chattering while performing NAND read. - Added by Srinivasa Wunnimani over 4 years ago

Hi,

I understand your point.
Please find the log attached for SD boot and NAND boot attached.

I am trying to explain with respect to line numbers in log file "u-boot_debug_with_SD_boot_and_NAND_boot.txt"

Line 1 to 97 is SD Boot:
No noise/chattering from line 102 to 117.

Programmed NAND chip from line 125 to 140

Did a reboot and performed NAND boot at line 145

Now I am in NAND BOOT.

I can hear the noise/chattering at line 276!!!

Next question:
I want to test the same with pre-built binaries for u-boot V2018.01.
Let me know where this is available at your end.

Regards
Srinivasa

u-boot_debug_with_SD_boot_and_NAND_boot.txt (5.23 KB) u-boot_debug_with_SD_boot_and_NAND_boot.txt

RE: GPIO toggling/chattering while performing NAND read. - Added by Jonathan Cormier over 4 years ago

Srinivasa Wunnimani wrote:

I want to test the same with pre-built binaries for u-boot V2018.01.
Let me know where this is available at your end.

Hmm just checked an looks like we haven't released the 2019 MDK which has u-boot 2018 yet. So we don't have any prebuilt binaries available.

I've attached the latest build from our build system. Which presumably would behave the same as your build.

U-Boot SPL 2018.01 (Nov 04 2019 - 22:02:57)

Download all files
MLO (60 KB) MLO (Nov 04 2019 - 22:02:57)
u-boot.img (473 KB) u-boot.img (Nov 04 2019 - 22:02:57)

RE: GPIO toggling/chattering while performing NAND read. - Added by Jonathan Cormier over 4 years ago

Srinivasa Wunnimani wrote:

Hi,

We have SOM board as per below link:

https://static6.arrow.com/aropdfconversion/bd95376e672d11c623e62dac62cb587c9bb1bc34/mitysom-335x-criticallink.pdf

If you have any evaluation board for the above mentioned SOM board, please perform below steps to simulate the problem:

1. Boot board from SD Card.
2. Flash NAND with below commands:

a. nand erase.chip
b. mmc rescan
c. fatload mmc 0 0x81000000 MLO
d. fatload mmc 0 0x81080000 u-boot.img
e. nand write 0x81000000 0x0 0x780000
f. saveenv

3. Reboot the board with NAND boot.
4. Perform NAND read with below command.

a. nand read.i 0x83000000 0x280000 0x500000

5. During NAND read, monitor GPIO 0_27 by probing.

This will help us to know if the issue is same across all hardware platform.

Regards
Srinivasa

What is your boot config for SD card boot and NAND boot? It would be the pull-up and pull-downs on the LCD_DATA0-11 pins.

RE: GPIO toggling/chattering while performing NAND read. - Added by Zafer Elbi over 4 years ago

Hello,
The last post was about 2 months ago. I am having exactly the same problem.
Our environment uses previous mityARM board (with single DDR2 version).
Before continuing further, I wondered if there has been any progress.
I tested the two images MLO and u-boot.img by Jonathan, but no change compared to my build.
Thanks

RE: GPIO toggling/chattering while performing NAND read. - Added by Jonathan Cormier over 4 years ago

Zafer Elbi wrote:

Hello,
The last post was about 2 months ago. I am having exactly the same problem.
Our environment uses previous mityARM board (with single DDR2 version).
Before continuing further, I wondered if there has been any progress.
I tested the two images MLO and u-boot.img by Jonathan, but no change compared to my build.
Thanks

Hi Zafer, just to confirm that the 2013.10 u-boot doesn't chatter but the 2018 one does?

RE: GPIO toggling/chattering while performing NAND read. - Added by Zafer Elbi over 4 years ago

Yes, exactly. We did that test before.
It doesn’t show up in 2013, but shows in 2018.
Thanks

From: <>
Sent: Tuesday, May 26, 2020 3:36 PM
Subject: [ARM Cortex-A8 Based Products - Software Development - msg5925] RE: GPIO toggling/chattering while performing NAND read.

[External Mail]

RE: GPIO toggling/chattering while performing NAND read. - Added by Zafer Elbi over 4 years ago

Have you had any chance to create the problem on your side, I mean since the discussion started?
ZE

From: Elbi, Zafer
Sent: Tuesday, May 26, 2020 4:04 PM
To: '' <>
Subject: RE: [ARM Cortex-A8 Based Products - Software Development - msg5925] RE: GPIO toggling/chattering while performing NAND read.

Yes, exactly. We did that test before.
It doesn’t show up in 2013, but shows in 2018.
Thanks

From: <mailto:> <<mailto:>>
Sent: Tuesday, May 26, 2020 3:36 PM
Subject: [ARM Cortex-A8 Based Products - Software Development - msg5925] RE: GPIO toggling/chattering while performing NAND read.

[External Mail]

RE: GPIO toggling/chattering while performing NAND read. - Added by Jonathan Cormier over 4 years ago

Zafer Elbi wrote:

Have you had any chance to create the problem on your side, I mean since the discussion started?
ZE

Sorry, a few fires came up and this got forgotten. We are currently looking to see if we can get the resources to reproduce this bug.

RE: GPIO toggling/chattering while performing NAND read. - Added by Jonathan Cormier over 4 years ago

Worked on this with Zafer. Posting this to tie up the public post.

The solution to this is to pinmux the gpio0_27 pin in the MLO as a gpio.

Note that all the AD pins will be driven as outputs during the ROM bootloader. This can not be avoided.

From the TRM:

ROM access.PNG (102 KB) ROM access.PNG
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