Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

HI Jack,

I suggest you head over to the Cyclone V Documentation page Altera web site for this information.

The documentation is extensive, and should provide the information you need.

-Mike

Hi Mike,

Can you provide for me the exact product number for the Micron SDRAM on board. I need information on the timing parameters for those memories.

Thanks!

Jack

Hi,

Can someone please get back to me on this?

Thanks!

Jack

I read through the section for the Cyclone V on the HPS-FPGA AXI and the manual for the SDRAM that we are using but I can't find any info so I would appreciate your help.

I can get data stored in one location of the memory. But when I change address I can't get the data stored in the location I want. I am only changing from one address to the next one. I made there is 160 ns at the first memory location. The problem is that nothing gets stored in the first memory location, but I can get data stored in the second (which is the last) memory location.

So my question is what exactly do I have to do get data stored in the memory location when I change address.

Thanks for your time!

Jack

Hi Jack,

Have you taken the SDRAM FPGA port out of reset? The register is called hps.sdr.ctrlgrp.fpgaportrst, the description can be found in HPS Addressmap

We have used the modular SGDMA for reading and writing to the HPS DDR. It can be downloaded from: Modular SGDMA. I'll try to create an example project that has the FPGA write a count pattern into the HPS DDR, in the next couple of days.

Dan

Hi Dan,

When would you be able to make the examples available?

Thanks!

Jack

Hey Jack,

My plan is to get it up Thursday afternoon. I currently have the FPGA side done but need to finish up the linux side and test it.

Dan

Jack,

I have created a new wiki section and have added the hps ddr example there. LINK

Dan

Hi Dan,

A couple of issues:

1. I am having trouble compiling the code. It's returning warnings and errors like such:

Warning (125092): Tcl Script File mityarm_5csx_dev_board/synthesis/mityarm_5csx_dev_board.qip not found
Error (12006): Node instance "u0" instantiates undefined entity "mityarm_5csx_dev_board"

2. I guess all I have to do to add my custom input is replace the counter then. How long does it take to send one set of data across the bridge? Is it just the clock speed (100 MHz)?

Thanks!

Jack

Hi Jack,

1) Hmm, I believe that error is from qsys generate not being run. Let me know if after running generate if that error still comes up.

2) Yes that is correct, it just needs follow the Avalon Stream Standard. That is true the data will be clocked in at 100MHz but the SDRAM controller has the ability to assert back pressure.

Dan

O of course! Can't believe something simple like that slipped my mind.

Thank you so much! Hope this works!

Jack

Beautiful Work! Thank you so much!

Jack

Hi,

Just a question with regarding sending these data as a package.

I know that the data in the package will be stored consecutively starting from the starting address.

But if that package is ended, and I start a second package where does the second package start at. Does it start at where the first one left off or the first packages' starting address.

Thanks again for all your support!

Jack

Hi Jack,

Each packet needs its own descriptor, unless you are using parked writes. The descriptor is what tells the SGDMA component where to write that packet to, so the second packet will stall until another descriptor is pushed onto the dispatchers descriptor list, which tells the SGDMA where to put that packet in memory.

Dan

Hi Dan,

What's parked write? Is that just writing to one address only?

Is the descriptor like an address line?

For our project, we have a signal (Data Ready) and whenever it goes to zero, there is a 16 bit data that comes in. I was thinking of using the Data Ready line as the clock for both the st_cnt_src and the dma_write_master. Does that sound alright or do you have some suggestions.

Jack

Hi Jack,

Park Writes – When set the dispatcher will continue to reissue the same descriptor to the write
master when no other descriptors are buffered.

Yup, the address is part of the descriptor along with control signals.

For more information about the SGDMA components there is a PDF under ip/SGDMA_dispatcher in the example I posted last week.

I would suggest attaching the data ready signal to the avalon stream's data valid signal instead and using what ever your normal clock domain is to run those components.

Dan

Hi Dan,

I'm changing the write address in the descriptor in the VHDL. But it's still only writing to the first address and not writing to the subsequent address that I changed to. Is there something else that I have to do to update the descriptor beside changing the address.

I have parked write turned off, I know that for sure, and the address is updating correctly I double checked that.

Thanks!

Jack

Hi again,

Just reading through the document. Do I have to set GO to '1' each time I update the descriptor?

Thanks!

Jack

Yes, you need to set the go bit so the dispatcher knows that the descriptor is ready to be read.

Dan

Hi Dan,

I'm confused about this, does the Go signal go to "0" after each transfer such that I have to toggle it back to "1"?

I tried doing that but it didn't work.

Could you provide exactly what needs to be done to send multiple packets?

Thanks!

Jack

Hi Dan,

Is there any timing diagram with the SGDMA? I want to control some of the signals directly in the FPGA.

Thanks!

Jack

The descriptors are pushed onto a descriptor FIFO that the dispatcher reads from to start each transaction. So with setting the go bit, the descriptor will be written on to this FIFO.

To send multiple packets you will have to push multiple descriptors into the dispatcher, one per packet.

The SGDMA uses avalon interfaces so it should follow the timing stated in the avalon spec. The SGDMA components reference page can be found here.

Dan

Hi Dan,

I'm still confused about this. Would it be possible to provide an example of multiple packets?

For example two packets each with a counter.

Thanks!

Jack

Hi Dan,

We figured it out last week. So we are fine with this for now.

Jack

Hi,

Do you have any write to HPS memory examples where I can send data into the memory in a continuous stream rather than a packet at a time?

Thanks!

Jack