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GPIO pins and muxing them as pull down
Added by Tim Troester 4 days ago
Hi,
We were hoping to get some clarification on the issue below for our own understanding. This isn't a problem for us, but we wanted greater understanding in case there are accommodations we need to make on our version of the carrier board.
This issue was observed on the Critical Link reference board using the P3 expansion connector.
We noticed that GPIO0_15 (P3 pin 3) & GPIO_16 (P3 pin 5) are not pulled down to 0 volts, even if they are muxed as PIN_INPUT_PULLDOWN. Instead they sit at 2.2 volts. If we leave them as floating or PIN_INPUT_PULLUP, they sit at 3.3 volts. If we mux GPIO0_17 (P3 pin 7) the same way it will be pulled to 0 volts. Is there something special about these pins, or have we configured them incorrectly? Below is part of our .dts file.
main_gpio_p3_pins_default: gpio-p3-pins-default {
pinctrl-single,pins = <
/* P3 Connector */
AM62X_IOPAD(0x003c, PIN_INPUT_PULLDOWN, 7) /* (M25) GPMC0_AD0.GPIO0_15 */
AM62X_IOPAD(0x0040, PIN_INPUT_PULLDOWN, 7) /* (N23) GPMC0_AD1.GPIO0_16 */
AM62X_IOPAD(0x0044, PIN_INPUT_PULLDOWN, 7) /* (N24) GPMC0_AD2.GPIO0_17 */
Tim
Replies (2)
RE: GPIO pins and muxing them as pull down - Added by Alex Gieson 3 days ago
Hi Tim!
The pins GPMC_AD0 (GPIO0_15) and GPMC_AD1 (GPIO0_16) are pulled up on the SOM, and GPMC_AD2 (GPIO0_17) is pulled down on the SOM. This is because these GPIOs are also bootmode pins.
From the AM62x Carrier Board Design Guide (section 3.4):
BOOTMODE[2..0] pins are strapped (via pullup / pulldown resistors) to a logic “011” on the MitySOM-AM62 as they set clock configuration for the AM62x which is fixed by the SOM design.
So the behavior you're describing can be explained by the internal pull down and external pull up creating a voltage divider resulting in 2.2V on the bootmode 0 and 1 pins.
RE: GPIO pins and muxing them as pull down - Added by Tim Troester 3 days ago
Alex,
Thank you for the explanation.
Tim
