question regarding pin assignments for SFP example project
Added by Maxim Kanevsky 2 days ago
Hello Critical Link support team!!!
I'm trying to make my own test project for 10Gb Ethernet IP based on your example project called: mitysom-a5e-ref-sfp
I compiled design and saw that the GTS Ethernet Hard IP not working. I'm looking at status signals and output clocks and see that they are wrong. I've played with simulation and found that this may happen if the SFP Ref. Clock (156.25MHz) not connected or has not accurate frequency.
I found something strange in pin assignements when following the a5e.qsf, Table 5 MitySOM-A5E Mini J1 Connector Pin-Out in 60-000087-MitySOM-A5E-Mini-Processor-Datasheet.pdf, 80-001748RI-2RevA_SCH.pdf
a5e.qsf Table 5 Connection on
Signal FPGA pin J1 Pin Carrier Board
------------------------------------------------------------
SFP_RX_P/N PIN_AR81/79 A41/40 GND
SFP_TX_P/N PIN_AT75/72 H49/48 DisplayPort_TX3_P/N
I followed Carrier Board scematics signals from J6 (SFP+ connector) and found that the proper pins for the SFP signals are following:
a5e.qsf Table 5 Connection on
Signal FPGA pin J1 Pin Carrier Board
------------------------------------------------------------
SFP_RX_P/N PIN_P81/79 A49/48 SFP_RX_P/N
SFP_TX_P/N PIN_Y81/79 B47/46 SFP_TX_P/N
Also, saw that in the schematics of Carrier Board, the CLK0 if U10 (Si5338B) is mentioned 150MHz, while in fact it is 156.25MHz, so the Reference Clock pin assignement BA66/69 is looks correct.
Despite of all my findings and fixes, the GTS Ethernet Core still not working.
Do you know why the pins assigned such a strange way in mitysom-a5e-ref-sfp and if this is corect?? If yes, I don't understand how this may work.
If you have more updated project with SFP, please give me a link.
Thanks,
Max
Replies (2)
RE: question regarding pin assignments for SFP example project - Added by Maxim Kanevsky 2 days ago
By the way, I've used 80-001748RI-2RevA_SCH.pdf (REV 2), so, I saw that I need to look at schematics REV 1.
RE: question regarding pin assignments for SFP example project - Added by Michael Williamson about 13 hours ago
Hi Maxim,
We are looking at it now and have similar concerns. We have not focused too much on the SFP+ port yet as we were delayed getting silicon for a while and we shuffled the transceiver lanes around between the -1 and -2 boards.
Are you working with a -1 board? I will see if I can get something going on that for you for the SFP+ port if you are stuck.
I am sorry for the confusion. There are not too many -1 boards in the wild as we have moved to the -2 revision going forward.
The U10 clocks were updated between rev -1 and rev -2 boards:
Rev -1:
Output Clock 0 Frequency (MHz) = 156.250000000
Output Clock 1 Frequency (MHz) = 150.000000000
Output Clock 2 Frequency (MHz) = 100.000000000
Output Clock 3 Frequency (MHz) = 20.000000000
Rev -2:
Output Clock 0 Frequency (MHz) = 150.000000000
Output Clock 1 Frequency (MHz) = 156.250000000
Output Clock 2 Frequency (MHz) = 100.000000000
Output Clock 3 Frequency (MHz) = 20.000000000
This was primarily due to the transceiver shuffling.
I am sorry for the confusion on this. I will circle back with you and your team once we sort out and retest the SFP+ design.
