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From 09/07/2010 to 10/06/2010

10/01/2010

11:00 AM FPGA Development: RE: TLK100 Ethernet
Mike,
FYI It was the bias resistor. There was a type in the BOM and a 49.9K was installed instead of a 4.99K. ...
John Mladenik

09/27/2010

04:24 PM FPGA Development: RE: TLK100 Ethernet
Mike
Just to be sure can you tell me how you pinned out the PCB footprint. Does it match this picture looking fr...
John Mladenik
03:57 PM FPGA Development: RE: TLK100 Ethernet

Mike,
After talking this out with our software guy we are convinced its as your said,one of two things. The con...
John Mladenik
03:49 PM FPGA Development: RE: TLK100 Ethernet
Power up the unit in your board. Stop at u_boot and type:... Michael Williamson
02:05 PM FPGA Development: RE: TLK100 Ethernet
The JTAG R's and connector are not installed.
I have the ethernet connected to my home switch.
I set the ...
John Mladenik
01:55 PM FPGA Development: RE: TLK100 Ethernet
Hi John,
It looks like the OMAP MII interface is not making it to your network. The 169.254.X.X network means tha...
Michael Williamson
01:12 PM FPGA Development: RE: TLK100 Ethernet
Here is the ip addrs when plugged into the Critial Link and IT WORKS
Critical Link dev IT WORKS
root@mityomapl138:~...
John Mladenik
12:26 PM FPGA Development: RE: TLK100 Ethernet
I didn't write them down I just typed them when he told me to. This was in u-boot. Once I typed them in I could pi... John Mladenik
07:31 AM FPGA Development: RE: TLK100 Ethernet
What were the software commands? If they involved setting the peripheral configuration in u-Boot, then they only nee... Michael Williamson

09/26/2010

11:13 PM FPGA Development: RE: TLK100 Ethernet
Does the Ethernet on the MityDSP need to be initialized for each new TLK100 it gets plugged into? This one was init... John Mladenik

09/25/2010

02:27 PM Software Development: RE: Clean Shutdown
I think the most important thing is to mount the root filesystem and any filesystem you have your executable on with ... Michael Williamson

09/24/2010

08:34 PM FPGA Development: RE: TLK100 Ethernet
hey would it be possible that we talk on the phone?
858-254-0008
John Mladenik
08:20 PM FPGA Development: RE: TLK100 Ethernet
That message is OK. You can set up ethernet to use MII or RMII (but not both, and you're using MII).
It looks lik...
Michael Williamson
08:06 PM FPGA Development: RE: TLK100 Ethernet
I saw this among the test
EMAC: MII PHY configured, RMII PHY will not be functional
I attached the whole text
John Mladenik
07:50 PM FPGA Development: RE: TLK100 Ethernet
Can you dump out the text from the boot sequence? Does the u-Boot locate the PHY (via the MDIO scan)?
-Mike
Michael Williamson
07:42 PM FPGA Development: RE: TLK100 Ethernet
OK I made all the changes and it still does not work. I now think there are only two difference between out circuits... John Mladenik
03:39 PM Software Development: Clean Shutdown
How do you recommend we handle shutdown of our embedded device in order to ensure the consistency of the Linux file s... William Fisher
12:02 PM Software Development: RE: LCD/Display questions
We were able to get the LCD going with no problem, BTW. We'll be using it for our demo next week.
Thanks for the h...
William Fisher

09/23/2010

04:35 PM FPGA Development: RE: TLK100 Ethernet
yes. you should add a pull-up. Michael Williamson
04:16 PM FPGA Development: RE: TLK100 Ethernet
Mike,
The green on the component means I used a different value cap or resistor. C216 is there but I used a 1uF c...
John Mladenik
03:46 PM FPGA Development: RE: TLK100 Ethernet
Hi John,
I think you need to tie the RESET line on the phy to the MII_RESET_N signal. The SYS_RESET_N does not ge...
Michael Williamson
03:23 PM FPGA Development: RE: TLK100 Ethernet
More information for you.
Attached is a comparison between the Critical link schematics and ours schematics. View...
John Mladenik
01:42 PM FPGA Development: TLK100 Ethernet
I know this is outside of your support area but I thought I would ask this in case you might have an idea of what to ... John Mladenik

09/22/2010

02:28 PM Software Development: RE: LCD/Display questions
You'll need a different FPGA image. You also need to load an additional module (for the touchscreen controller on th... Michael Williamson
02:26 PM Software Development: RE: LCD/Display questions
Yup. That did it.
For some reason, I had copied the instructions for the Rev. C board instead of the ones above.
...
William Fisher
02:05 PM Software Development: RE: LCD/Display questions
Ah. OK. You punched in the i2c commands for the Rev C board. You have 0x3f programmed into position 0x08.
Please...
Michael Williamson
01:53 PM Software Development: RE: LCD/Display questions
I added a simple test pattern generator to the wiki [[LCD_configuration]]. It draws a white box around the border of ... Tim Iskander
01:50 PM Software Development: RE: LCD/Display questions
Done. Here's what I see:
0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
00: 4c 01 10 04 ...
William Fisher
08:17 AM Software Development: RE: LCD/Display questions
After you are up and running, could you please run a... Michael Williamson

09/21/2010

04:16 PM Software Development: RE: LCD/Display questions
Definitely not a Rev C board, so it must be a B (I think we have an A here as well, but this isn't it).
Yes, actua...
William Fisher
03:22 PM Software Development: RE: LCD/Display questions
Can you please confirm the revision of your board (B, or C)?
Before you write to the /dev/fb0 device, do you see a...
Michael Williamson
03:13 PM Software Development: RE: LCD/Display questions
Got it working. A few oddities, but I'm now able to at least talk to the frame buffer.
The screen is all blue and ...
William Fisher
10:07 AM Software Development: RE: LCD/Display questions
William
If you are seeing blue vertical stripes (every other pixel) then the frame buffer is working..
try the foll...
Tim Iskander

09/20/2010

10:53 PM Software Development: RE: LCD/Display questions
OK -- we're definitely making progress here. I now see a raster on the DVI-based monitor. It's just vertical blue str... William Fisher
09:37 PM Software Development: RE: LCD/Display questions
Got it. I'll check this out right now and let you know what happens. William Fisher
08:08 PM Software Development: RE: LCD/Display questions
That's the right image. All the files show up at the bottom of the wiki.
I've updated the wiki with more instru...
Michael Williamson
02:23 PM Software Development: RE: LCD/Display questions
I downloaded the file "IndustrialIO_dvi_revA-B.bin" and used it to program the FPGA (in Linux, using the instructions... William Fisher
11:56 AM Software Development: RE: LCD/Display questions
We'll take a look at this setup today and let you know what happens.
The next thing we'll want to know is what com...
William Fisher

09/17/2010

06:32 PM Software Development: RE: LCD/Display questions
It's off the [[Das_U-Boot_Port]] page from the start page. I'll look at making another entry.
Michael Williamson
06:06 PM Software Development: RE: LCD/Display questions
Could you put the link to that wiki page into the wiki start page please. Dennis Volper
05:52 PM Software Development: RE: LCD/Display questions
The [[LCD configuration]] wiki page has been started that will cover the information you need. It's a work in progre... Michael Williamson
02:27 PM FPGA Development: RE: How to implement bidirectional BLVDS in the FPGA (Spartan-6 )
I received a reply back from Xilinx tech support.
They indicated that the approach for Spartan-6 would be similar ...
Dene Olsen

09/16/2010

08:26 PM Software Development: RE: LCD/Display questions
I'll need a little more information about the uboot to be able to have it tell the kernel to initialize the device. A... Dennis Volper
07:01 PM Software Development: RE: LCD/Display questions
Mr. Schlunk,
The kernel included in the development kit provided should have the necessary code installed to suppo...
Michael Williamson
06:33 PM Software Development: LCD/Display questions
We are trying to figure out how to get video out of the board and had a couple of questions.
Does your development...
Otmar Schlunk
04:36 PM FPGA Development: How to implement bidirectional BLVDS in the FPGA (Spartan-6 )
I need to implement a data bus as part of an interface to the Xilinx FPGA, and it must be a bidirectional BLVDS inter... Dene Olsen

09/07/2010

04:12 PM FPGA Development: RE: Critical link bit file
Actually John,
you shouldn't need to reprogram the NAND/root filesystem. Only the kernel. The NAND should still ...
Michael Williamson
04:10 PM FPGA Development: RE: Critical link bit file
Right. The procedure you just ran only reloads the bootloader images.
You will also need to reload the kernel i...
Michael Williamson
04:03 PM FPGA Development: RE: Critical link bit file
it gets into uboot but once past uboot I get this
8192 KiB M25P64 at 0:0 is now current device
Wrong Image Format...
John Mladenik
04:01 PM FPGA Development: RE: Critical link bit file
that worked I am backup and running.
thanks
John
John Mladenik
03:52 PM FPGA Development: RE: Critical link bit file
Hi John,
I copied the instructions wrong from our factory programming instruations. Sorry. The "-c" option shoul...
Michael Williamson
03:43 PM FPGA Development: RE: Critical link bit file
I ran this exactly how you said and I get the usage for the command here is what I typed in
sfh_OMAP-L138 -flash ...
John Mladenik
01:38 PM FPGA Development: RE: Critical link bit file
Look at the [[Reprogramming a Dead Board]] wiki link. Let me know if you run into trouble.
-Mike
Michael Williamson
01:18 PM FPGA Development: RE: Critical link bit file
It was my fault not yours so no big deal. If you can post what it takes to re-flash the boot code. If this doesn't... John Mladenik
07:54 AM FPGA Development: RE: Critical link bit file
Hi John,
Well, the bad news is that I think you whacked the bootloading code on the SPI FLASH.
The "sf write" c...
Michael Williamson
07:57 AM Software Development: RE: Audio help needed
Hi Otmar,
The API will be ALSA.
My best guess would be something mid-October. We'll try to bump it up on the p...
Michael Williamson
 

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