Activity
From 07/15/2011 to 08/13/2011
08/12/2011
- 07:07 AM FPGA Development: RE: 372 MHz
- Hi Rob,
In general, running at different EMIFA bus rates should be OK as long as you keep in mind the following po...
08/11/2011
- 06:23 PM Software Development: RE: git connection
- Thomas
We were having some issues with our server earlier today. It should be all better now.
cheers
/Tim - Hi,
How are you doing ?
I was following the steps listed here:
http://support.criticallink.com/redmine/projects/a... - Hello,
I am running my L138 CPU at 372 MHz, which results in the EMIFA bus running at 93MHz instead of 100 MHZ.
...
08/09/2011
- 03:38 PM Software Development: RE: Using the EMIFA to read/write FPGA registers
- It worked! I changed to 0x40 and used 16 bit numbers. Here's the new code that worked-
UInt32 *Fpga_mem_ptr = (un... - 02:30 PM Software Development: RE: Using the EMIFA to read/write FPGA registers
- Well, OK.
If you are using our framework with the base module, the address at offset zero corresponds to a read on... - 02:09 PM Software Development: RE: Using the EMIFA to read/write FPGA registers
- I tried to use the following code to write and read from a register. I used both CS4 and CS5 (0x64000000 and 0x660000...
- 12:19 PM Software Development: RE: Using the EMIFA to read/write FPGA registers
- Well the wiki says CS5 is used for the DSP, but when I look at the VHDL it says CS4.
- 12:15 PM Software Development: RE: Using the EMIFA to read/write FPGA registers
- Marc,
Are you using CS4 or CS5?
0x66000000 corresponds to CS5.
-Mike
- 12:04 PM Software Development: RE: Using the EMIFA to read/write FPGA registers
- So does the EMIFA just run in the background and constantly refresh the values? Or does it perform an action when yo...
- 11:55 AM Software Development: RE: Using the EMIFA to read/write FPGA registers
- Hi Marc,
The FPGA registers are memory mapped starting at DSP address 0x66000000. The registers for each additiona... - Hey All,
I am trying to access the FPGA registers using the EMIFA, but I am having trouble finding documentation e... - 03:36 PM Software Development: RE: continual reboot
- @sfh_OMAP-L138 -erase -p COM7@ worked!!
- 03:00 PM Software Development: RE: continual reboot
- Should. You'll need to reflash again the u-Boot and UBL. Give it a try. (good catch, BTW).
-Mike
- 02:49 PM Software Development: RE: continual reboot
- Would this work?
sfh_OMAP-L138 -erase
help sez:
Global erase of the flash memory device (no input files) - 02:46 PM Software Development: RE: continual reboot
- Argh. The SPI reprogramming doesn't wipe the u-Boot environment or the FPGA environment, so it just picks back up wh...
- 02:41 PM Software Development: RE: continual reboot
- Control-C does not work. Tried in both HyperTerminal and Putty.
Also tried dead board instructions with seemingly ... - 02:33 PM Software Development: RE: continual reboot
- Try hitting control-C continuously while booting. If that does not work, you can use the "programming a dead board" ...
- Hi,
I modified the FPGA code and during the write the board rebooted.
I had bootfpga set to load the fpga automat...
08/08/2011
- 10:59 AM Software Development: RE: Mounting USB Flash Memory (mitydspl138)
- Hi Fred,
Most likely the *USB Mass Storage support* option is not selected in the config for the kernel you're usi...
08/05/2011
- I have the mitydspl138, baseboard, and the standard Critical Link Linux kernel. When I plug a usb flash drive into th...
08/03/2011
- 10:17 AM FPGA Development: RE: Programming the FPGA
- The pwm.ngc should be included in the 2011-08-01 MDK release (just published).
-Mike
- 09:41 AM FPGA Development: RE: Programming the FPGA
- I successfully built this project but I had to comment out anything related to pwm. Seems I do not have the pwm.ngc n...
07/29/2011
- 11:37 AM FPGA Development: RE: Programming the FPGA
- Thanks Mike. I picked up the common VHDL files with no trouble.
However, when I tried to add a netlist file (.ngc?... - 07:30 AM FPGA Development: RE: Programming the FPGA
- Hi Craig,
Yeah, the Xilinx ISE file format really doesn't use relative path names very well.
As far as the VHDL...
07/27/2011
- 05:28 PM Software Development: RE: NAND controller, EDMA3 and EMIFA priorities
- Hi Mads,
I'm not sure there is much more you can do than what is already configured.
You might consider cross p... - Hi
I have a few questions regarding the NAND flash and EMIFA.
From the EDMA priority settings below (which I ju... - 05:05 PM Software Development: RE: Mapping code to IRAM
- Hi Mark
You could try the #pragma CODE_SECTION(<function name>, "mysect") (In C++ you omit the function name and p...
07/26/2011
- 05:14 PM Software Development: RE: Mapping code to IRAM
- Hi Marc -
I'm not sure we will have the answer to this question as it's really a TI question. While we're waiting... - Hey All,
I am using CCS4 and SYS/BIOS to program the DSP core in the L138, and I am trying to figure out how to sp... - 09:43 AM FPGA Development: RE: Programming the FPGA
- I opened this project file in XISE and it yelled at me for a number of VHD files (see attached png).
example.zip -...
07/24/2011
- 08:44 PM FPGA Development: RE: Programming the FPGA
- Success has been achieved. Thanks Mike!
I loaded the stock uImage from the .run file supplied with the kit. That d... - 12:55 PM FPGA Development: RE: Programming the FPGA
- Hi Craig,
I think you need to modify the bootargs assuming the NAND has a valid filesystem on it.
See "this wik... - 09:45 AM FPGA Development: RE: Programming the FPGA
- The uImage_Indio_20110723 kernel image booted but could not mount to a filesystem.
Getting closer!
I attached t...
07/23/2011
- 12:52 PM FPGA Development: RE: Programming the FPGA
- Thanks Mike.
My plan is to also extract the image from the .run file and try both this afternoon.
I am using th... - 11:40 AM FPGA Development: RE: Programming the FPGA
- Hi Craig,
I am attaching a uImage file built for the Industrial I/O board from our kernel code baseline.
This r... - 10:57 AM FPGA Development: RE: Programming the FPGA
- Hey Mike,
Late yesterday I booted into UBOOT; cleared the bootfpga (setenv bootfpga;saveenv); rebooted with Angstr... - 09:04 AM FPGA Development: RE: Programming the FPGA
- Hi Craig,
Just following up. Are you still DOA? Or did not programming the FPGA clear the issue?
-Mike
07/22/2011
- 01:24 PM FPGA Development: RE: Programming the FPGA
- Good point. I'll defer any FPGA programming until I resolve the linux kernel load.
Here's the boot text. You can s... - 01:14 PM FPGA Development: RE: Programming the FPGA
- Also,
Can you dump the entire boot text from power up to hang? Would like to see all the commands executed by the... - 01:13 PM FPGA Development: RE: Programming the FPGA
- Hi Craig,
Are you programming the FPGA before you load the kernel? The FPGA can cause problems with the kernel lo... - 01:06 PM FPGA Development: RE: Programming the FPGA
- I tried again in case I screwed up the first time.
I also tried the uImage file in /boot on another of our boards....
07/21/2011
- 05:00 PM FPGA Development: RE: Programming the FPGA
- Hi Greg,
Thanks for XISE files.
I followed instructions from Linux Kernel installtion using uImage from files a... - 02:03 PM FPGA Development: RE: Programming the FPGA
- Hi Craig,
I've attached the project file used to build the .bin file I posted earlier. You'll need to link against... - 02:02 PM FPGA Development: RE: Programming the FPGA
- The revised read instruction works!
We have the L138-FI-225-RC. My mistake. I was looking at the wrong line in the... - 01:43 PM FPGA Development: RE: Programming the FPGA
- Hi Craig,
For the bootgpga image, you need to read out all of the image into RAM before trying to program the FPGA... - 01:03 PM FPGA Development: RE: Programming the FPGA
- Question on automatically loading the FPGA at boot...
I've followed these instructions:
loadb 0xC0700000
[send... - 12:21 PM FPGA Development: RE: Programming the FPGA
- Can you guys zip up and post or e-mail me source files used to generate this .bin?
I would like to play some with ... - 11:09 AM FPGA Development: RE: Programming the FPGA
- Hi Tim.
I'm on my 3rd USB-to-serial adapter and 4th attempt at driver update. I'm sure some manager got a nice bon... - 10:15 AM FPGA Development: RE: Programming the FPGA
- Hi Tim,
Do I need a different version of SPIWriter_MityDSP-L138.out? Didn't see this file in the latest zip.
I ... - 09:07 AM FPGA Development: RE: Programming the FPGA
- Craig
I have uploaded the latest serial programming utility to the files section.
Try that and see if it corrects ... - 08:22 AM FPGA Development: RE: Programming the FPGA
- I've tried several other usb to serial adaptors with no luck.
I get the same error:
(AIS Parse): Performing Opco...
07/20/2011
- 12:10 PM FPGA Development: RE: Programming the FPGA
- Yes. I'm using USB to serial dongle. It's unbranded using Prolific chipset. Unfortunately I do not have a "real" seri...
- 10:43 AM FPGA Development: RE: Programming the FPGA
- Craig
I see your serial port is COM7.. I presume that is a USB serial dongle? What brand / model is it? We have had ... - 10:25 AM FPGA Development: RE: Programming the FPGA
- Tried dead board instructions (sfh_OMAP-L138 -flash -v -p COM7 UBL_SPI_MEM.ais u-boot.bin) and I get read error:
(... - 09:01 AM FPGA Development: RE: Programming the FPGA
- Craig
If you set the bootfpga environment var, uboot will automatically run the commands at startup. I'm not exactly... - 08:57 AM FPGA Development: RE: Programming the FPGA
- Good news / bad news.
It was a successful load. Green DONE led lit.
However, I apparently hammered the flash wi...
07/19/2011
- 05:06 PM FPGA Development: RE: Programming the FPGA
- Hi Craig,
I've attached a .bin file that should work for you (in the future we will add LX45 example .bin files to... - 02:49 PM FPGA Development: RE: Programming the FPGA
- Hi Greg.
This command worked: U-Boot > sf erase 0x580000 0x170000
But you are right. I still have issues.
I ... - 01:50 PM FPGA Development: RE: Programming the FPGA
- Hi Craig,
The flash erase needs to be page aligned. This should work:... - 01:22 PM FPGA Development: RE: Programming the FPGA
- Tim - I think we are getting close.
Here's the result:
U-Boot > sf erase 0x580000 0x16b000
SPI flash erase failed - 12:53 PM FPGA Development: RE: Programming the FPGA
- Craig
Aha!
The default size for uboot's loadfpga command (and what is shown on the wiki!) is 0x80000 (1/2MB), whic... - 11:49 AM FPGA Development: RE: Programming the FPGA
- Thanks Tim.
No DONE led yet but looks as if I made progress:
U-Boot > sf probe 0; sf read 0xc0700000 0x580000 ... - 11:43 AM FPGA Development: RE: Programming the FPGA
- Craig,
another thing to check is that the configuration of the device is correct.
if you run factoryconfig at the U... - 11:32 AM FPGA Development: RE: Programming the FPGA
- Craig
The DONE led should go on immediately after programming the FPGA.
Can you try running the commands in the boo... - I'm following these Wiki instructions and I'm not getting the DONE led:
U-Boot > loadb 0xC0700000
## Ready for bi...
07/15/2011
- 11:18 AM Software Development: RE: MityDSPl138 JTAG
- Marc,
Try stopping the ARM in the u-Boot phase and see if you can connect to the DSP then. The linux portion of A... - Hey All,
I have the XDS100V1 JTAG emulator, and I'm trying to connect to the DSP core with CCS4, but it does not s... - 07:17 AM Software Development: RE: MITYDSP OMAP-L138 EMIF FPGA / NAND shared bus access
- Hi Mike
I have a few questions regarding the NAND flash and EMIFA.
As you earlier mentioned I could try adjusti...
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