Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

06/24/2019

04:38 PM Software Development: RE: uPP receive clock lower limitation in SDR (Single Data Rate mode)

Hi Vivek,
I believe the datasheet is saying that regardless of whether the clock is being used as DDR or SDR the ... Gregory Gluszek

06/21/2019

08:05 AM Software Development: uPP receive clock lower limitation in SDR (Single Data Rate mode)

Hi,
I have a custom board with
-- MityDspl-138F module (with FPGA)
-- No Ethernet port
-- UART,USB,SD CARD int... Vivek Ponnani

06/06/2019

03:12 PM Software Development: RE: MityDSPL138

VIDYA J wrote:
> But in CCS they are asking initialization file for the processor.
When your building? Jonathan Cormier

03:10 PM Software Development: RE: MityDSPL138

But in CCS they are asking initialization file for the processor. VIDYA J

01:16 PM Software Development: RE: MityDSPL138

VIDYA J wrote:
> I used UART_echo code from OMAPL138_StarterWare_1_10_03_03 folder. For coding ARM i read like i nee... Jonathan Cormier

06:13 AM Software Development: RE: MityDSPL138

I used UART_echo code from OMAPL138_StarterWare_1_10_03_03 folder. For coding ARM i read like i need to add gel file.... VIDYA J

06/04/2019

01:47 PM Software Development: RE: MityDSPL138

VIDYA J wrote:
> For my project i want to do inter process communication on omapl138. Please reply for my below doub... Jonathan Cormier

07:16 AM Software Development: MityDSPL138

For my project i want to do inter process communication on omapl138. Please reply for my below doubts
1. Is there Li... VIDYA J

05/28/2019

09:10 AM Software Development: uPP channel B in receives mode missing data from FPGA

Hi,
I have a custom board with
-- MityDspl-138F module (with FPGA)
-- No Ethernet port
-- UART,USB,SD CARD int... Vivek Ponnani