Project

General

Profile

Activity

From 07/08/2019 to 08/06/2019

07/22/2019

01:34 PM Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal)
Aviv Prital wrote:
> Hi, thanks for reply!
> Two follow up questions:
> Concerning "you may want to look at some o...
Jonathan Cormier

07/18/2019

06:00 AM Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal)
Hi, thanks for reply!
Two follow up questions:
Concerning "you may want to look at some of the DSPlink or syslink c...
Aviv Prital

07/17/2019

03:04 PM Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal)
Note if your writing your own bare-metal communication you may want to look at some of the DSPlink or syslink code as... Jonathan Cormier
02:05 PM Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal)
Thanks for the prompt reply!
I'm thinking about shared RAM that ARM user space linux driver will be able to mmap in ...
Aviv Prital
02:01 PM Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal)
Could you provide more information on what is suitable for your project? Jonathan Cormier
01:44 PM Software Development: Change data between ARM(Linux) - DSP (bare-metal)
Hi,
I'd like to use MityDSPL138 kit in order to develop ARM(Linux) - DSP (bare-metal) data exchange over shared memo...
Aviv Prital

07/08/2019

02:57 PM FPGA Development: Reference Project AnalogExpansionSuite query
Hi,
I have a custom board with
-- MityDspl-138F module (with FPGA)
-- No Ethernet port
-- UART,USB,SD CARD int...
Vivek Ponnani
10:05 AM Software Development: RE: uPP receive clock lower limitation in SDR (Single Data Rate mode)
Thanks Greg for your reply and sorry for the late reply.
I will forward your response to our FPGA team. They are u...
Vivek Ponnani
 

Also available in: Atom

Go to top
Add picture from clipboard (Maximum size: 1 GB)