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From 05/18/2024 to 06/16/2024

06/10/2024

11:08 AM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem
There is a cross-bar that sits between EMIFA on the L138 and the DSP / ARM / peripheral masters.
When a read reque...
Michael Williamson
07:52 AM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem
Thank you for answer.
We will conduct the above experiment later.
Currently, we are trying to increase the RD Clk...
Kyungguk Bok

06/05/2024

09:05 PM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem
Hello,
Based on the FPGA code you shared I believe that the primary issue you are having is that your FPGA code r...
Gregory Gluszek
12:42 AM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem
Thank you for answer.
As you suggested, read Cache_and_Memory and
We proceeded by modifying the source as shown bel...
Kyungguk Bok

06/03/2024

03:08 PM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem
The fpga guys can step in if I've missed something but it looks to me like your missing cache invalidate calls. If t... Jonathan Cormier
08:57 AM Software Development: FPGA (FIFO) -> DSP (DMA) transfer problem
hello.
I am posting because I have a question related to DMA.
The last CCS issue was not resolved, so I am loading ...
Kyungguk Bok
 

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