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From 07/04/2024 to 08/02/2024

07/29/2024

JC 05:36 PM PCB Development: RE: X1 component SiLabs 590 BA100M000G depopped
See "PCN20220621000":https://support.criticallink.com/redmine/attachments/download/31707/PCN20220621000.pdf linked from https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Module_Product_Change_Notifications
This osc...
Jonathan Cormier
RS 02:09 PM PCB Development: X1 component SiLabs 590 BA100M000G depopped
Hello,
we are working on transferring our design from the Spartan 6 build to the A7 SOM and an engineer noticed noticed that the X1 oscillator is depopped on our A7 builds. Can you confirm what this oscillator does, and if it is for ...
Rachel Shaska

07/24/2024

FW 02:31 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early
I figure it's about 10% of the CPU when operating 1200 baud and 1 response per second; it gets much lower as you approach 9600 baud (1.3%). This also takes into account the modulo 16 fifo calc assuming random packet lengths. All in all, ... Fred Weiser

07/22/2024

JC 07:21 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early
> before shutting off the 485 driver
Any idea how often the shutting down occurs?
Jonathan Cormier
FW 07:19 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early
I patched the 8250.c file to increase the 10ms timeout. I found the timeout is really there only to assure the uart tx fifo drains completely before shutting off the 485 driver - as such, it will never be more than about 16 characters. I... Fred Weiser

07/19/2024

DL 06:14 PM PCB Development: RE: MityDSP-L138F Block Diagram Inconsistencies
Dan,
That clears things up perfectly. Thank you for a quick and comprehensive response.
Dylan Louviaux
DV 06:10 PM PCB Development: RE: MityDSP-L138F Block Diagram Inconsistencies
Hi Dylan,
The external input to the Boot Config Block is the EXT_BOOT# signal pin bin 12 of the SO-DIMM connector. The Boot Config Block on the SOM uses the value of EXT_BOOT# to set the boot strap resistors for the L138. The two opti...
Daniel Vincelette
DL 04:06 PM PCB Development: MityDSP-L138F Block Diagram Inconsistencies
All,
I am designing a carrier board for the MityDSP-L138F with A7 FPGA. I have noticed some inconsistencies with the block diagrams in the documentation (https://www.criticallink.com/wp-content/uploads/2014/01/MityDSP-L138F_Spec.pdf).
...
Dylan Louviaux
 

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