FPGA Developers' Guide¶

FPGA Resources¶

All files needed to develop a new FPGA design for the MityDSP-L138F or MityAM-1808F SOMs are included in the Board_Support_Package download under the "fpga/vhdl" directory. If you have an Industrial I/O baseboard (a "developer's kit" baseboard), then there is also an example project located in the "examples/industrial_io/fpga" directory.

The most commonly sought after file is the UCF template under "fpga/vhdl/MityDSP_L138.ucf". This file includes constrains definitions for all the pins on the FPGA as routed to the processor or to the edge connector. Most of the constraints are commented out, you'll need to locate the pins you want to use and un-comment the constraint (and likely renaming the pin name to be specific to your design).

Warning: The template UCF file specifies a 100 MHz EMIFA clock rate. If you alter the CPU speed from the default 300 MHz operating point, the EMIFA clock (EMA_CLK) may run at a slightly higher rate, and the EMA clock will stop and restart when the CPU frequency settings are changed. If you are using a DCM, this will result in the lock being broken and a reset must be applied to the DCM. It is recommended that the FPGA be loaded after CPU frequency settings have been applied, if this is possible. You should also carefully determine the proper timing constraint on this pin based on your final clock configuration for the EMIFA subsystem.

Xilinx Tool Chain Settings and Gotchas¶

At this time we recommended Xilinx ISE version 14.X.

It is available for download from this link at Xilinx: http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools.html

Synthesis Properties
Some recommended settings for synthesis are listed below.¶

• HDL Options > Shift Register Extraction / Minimum Size :
  Should probably be disabled or set higher if registers are used to help meet timing. Use a minimum of 3 for shift register extraction.

• Xilinx Specific Options > Pack I/O Registers into IOBs :
  Leave set to "Auto" or force to "Yes".

Map Properties
Some recommended settings for map are listed below.¶

• Global Optimization :
  Leave at default "Off" setting unless you know what you are doing.
  Enabling can override Synthesis options/actions such as turning off shift-register extraction (global or signal-specific).

• Pack I/O Registers/Latches into IOBs :
  Should be set to "For Inputs and Outputs".

Generate Programming File Properties
Some recommended settings for bitfile generation are listed below.¶

• Configuration Options > Unused IOB Pins :
  Should usually be set to "Float". Other options can be used if the carrier board(s) are well understood.

Creating a FPGA Image for Software Programming¶

The FPGA image file required for software programming is not in the same format as the legacy MityDSP FPGA images. The MityDSP-L138 family of SOM's require a bit-swapped binary (BIN) file generated in byte wide words. To create a prom file that is supported by the SOMs, run the following command from a command line, or from within a script:

promgen -p bin -u 0 input.bit -o output.bin

Note, this command assumes that the Xilinx promgen utility is in the system path.

EMIFA Framework Information¶

The EMIFA framework interface is described on the EMIF_Interface page.