The GPIO Core¶

This is a documentation page for using the Critical Link GPIO core.

• The FPGA GPIO Core pins start at pin #144 on the Linux side of things.
• So pin #144 will map to the first gpio in the first gpio core. The gpio core will then be connected to a net name which gets mapped to a fpga pin name in the .ucf file. See $MDK/examples/industrial_io/fpga/vhdl/IndustrialIO_rev_C.ucf for example.

Component Instantiation¶

There are effectively three scenarios in which the GPIO core can be instantiated:

1. GPIOs as Inputs
   

   GPIO_INST : gpio
       generic map 
       (
           NUM_BANKS       => 1,
           NUM_IO_PER_BANK => 16
       )
       port map 
       (
           clk => ema_clk,
           i_ABus => addr_r,
           i_DBus => edi_r,
           o_DBus => edo5(CORE_GPIO),
           i_wr_en => wr_r,
           i_rd_en => rd_r,
           i_cs => cs5_r(CORE_GPIO),
           o_irq => irq_map(CORE_GPIO_LVL)(CORE_GPIO_VEC),
           i_ilevel => conv_std_logic_vector(CORE_GPIO_LVL, 2),
           i_ivector => conv_std_logic_vector(CORE_GPIO_VEC, 4),
           i_io => i_gpio, -- GPIO read values
           t_io => open, -- Direction of GPIOs
           o_io => open, -- GPIO write values
           i_initdir => x"0000", -- default to all inputs
           i_initoutval => x"0000" 
       );
   

2. GPIOs as Outputs
   

   GPIO_INST : gpio
       generic map 
       (
           NUM_BANKS       => 1,
           NUM_IO_PER_BANK => 16
       )
       port map 
       (
           clk => ema_clk,
           i_ABus => addr_r,
           i_DBus => edi_r,
           o_DBus => edo5(CORE_GPIO),
           i_wr_en => wr_r,
           i_rd_en => rd_r,
           i_cs => cs5_r(CORE_GPIO),
           o_irq => irq_map(CORE_GPIO_LVL)(CORE_GPIO_VEC),
           i_ilevel => conv_std_logic_vector(CORE_GPIO_LVL, 2),
           i_ivector => conv_std_logic_vector(CORE_GPIO_VEC, 4),
           i_io => s_gpio, -- GPIO read values. Loop back output values so they can be read from software.
           t_io => open, -- Do not care about direction of GPIOs
           o_io => s_gpio, -- GPIO write values
           i_initdir => x"FFFF", -- default to all outputs
           i_initoutval => x"0000" 
       );
   
       -- Set output ports
       o_gpio <= s_gpio;
   

3. GPIOs as Bidirectional Inputs and Outputs
   

   GPIO_INST : gpio
       generic map 
       (
           NUM_BANKS       => 1,
           NUM_IO_PER_BANK => 16
       )
       port map 
       (
           clk => ema_clk,
           i_ABus => addr_r,
           i_DBus => edi_r,
           o_DBus => edo5(CORE_GPIO),
           i_wr_en => wr_r,
           i_rd_en => rd_r,
           i_cs => cs5_r(CORE_GPIO),
           o_irq => irq_map(CORE_GPIO_LVL)(CORE_GPIO_VEC),
           i_ilevel => conv_std_logic_vector(CORE_GPIO_LVL, 2),
           i_ivector => conv_std_logic_vector(CORE_GPIO_VEC, 4),
           i_io => io_gpio, -- GPIO read values
           t_io => t_gpio, -- Direction of GPIOs
           o_io => o_gpio, -- GPIO write values
           i_initdir => x"FFFF", -- default to all outputs
           i_initoutval => x"0000" 
       );
   
   -- Process to drive inout ports when GPIO core is in output mode or set to high Z when GPIO core is in input mode
   GEN_GPIO_IOBS : for i in 0 to 15 generate
   begin
      io_gpio(i) <= o_gpio(i) when t_gpio(i) = '0' else 'Z';
   end generate GEN_GPIO_IOBS;