Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

12/23/2013

10:46 AM FPGA Development: RE: I/O voltage

No problem, it can wait a while.
Sounds like the SOM may have been catered for. Any thoughts on the dev kit or do ... Nigel Doe

09:03 AM FPGA Development: RE: I/O voltage

Hi Nigel,
The best guy to answer this question is on break this week and a good chunk of next week, can you wait f... Michael Williamson

08:15 AM FPGA Development: I/O voltage

I would like to interface the MityARM-5C SX dev kit to an existing piece of equipment for evaluation purposes, howeve... Nigel Doe

12/16/2013

12:23 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
We figured it out last week. So we are fine with this for now.
Jack Anonymous

12/12/2013

05:17 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
I'm still confused about this. Would it be possible to provide an example of multiple packets?
For exam... Anonymous

12/10/2013

06:36 PM FPGA Development: RE: HPS Memory Controller

The descriptors are pushed onto a descriptor FIFO that the dispatcher reads from to start each transaction. So with s... Daniel Vincelette

05:18 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
Is there any timing diagram with the SGDMA? I want to control some of the signals directly in the FPGA.
... Anonymous

04:49 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
I'm confused about this, does the Go signal go to "0" after each transfer such that I have to toggle it ba... Anonymous

04:28 PM FPGA Development: RE: HPS Memory Controller

Yes, you need to set the go bit so the dispatcher knows that the descriptor is ready to be read.
Dan Daniel Vincelette

12:17 PM FPGA Development: RE: HPS Memory Controller

Hi again,
Just reading through the document. Do I have to set GO to '1' each time I update the descriptor?
Than... Anonymous

12:12 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
I'm changing the write address in the descriptor in the VHDL. But it's still only writing to the first add... Anonymous

12/09/2013

03:53 PM FPGA Development: RE: HPS Memory Controller

Hi Jack,
Park Writes – When set the dispatcher will continue to reissue the same descriptor to the write
master w... Daniel Vincelette

03:37 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
What's parked write? Is that just writing to one address only?
Is the descriptor like an address line?
... Anonymous

02:26 PM FPGA Development: RE: HPS Memory Controller

Hi Jack,
Each packet needs its own descriptor, unless you are using parked writes. The descriptor is what tells th... Daniel Vincelette

02:15 PM FPGA Development: RE: HPS Memory Controller

Hi,
Just a question with regarding sending these data as a package.
I know that the data in the package will be... Anonymous

12/06/2013

03:14 PM FPGA Development: RE: HSMC to GPIO

Hi Jack,
The 5CSX dev board follows the Altera defined pinout for HSMC so that should work.
Dan Daniel Vincelette

03:00 PM FPGA Development: HSMC to GPIO

Hi,
Is HSMC on base board laid out the same pin out as this particular Terasic daughter board (this is what Altera... Anonymous

12/05/2013

06:14 PM FPGA Development: RE: HPS Memory Controller

Beautiful Work! Thank you so much!
Jack Anonymous

05:57 PM FPGA Development: RE: HPS Memory Controller

O of course! Can't believe something simple like that slipped my mind.
Thank you so much! Hope this works!
Jack Anonymous

05:51 PM FPGA Development: RE: HPS Memory Controller

Hi Jack,
1) Hmm, I believe that error is from qsys generate not being run. Let me know if after running generate i... Daniel Vincelette

05:35 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
A couple of issues:
1. I am having trouble compiling the code. It's returning warnings and errors like ... Anonymous

03:34 PM FPGA Development: RE: HPS Memory Controller

Jack,
I have created a new wiki section and have added the hps ddr example there. "LINK":http://redmine.criticalli... Daniel Vincelette

12/04/2013

08:23 PM FPGA Development: RE: HPS Memory Controller

Hey Jack,
My plan is to get it up Thursday afternoon. I currently have the FPGA side done but need to finish up th... Daniel Vincelette

05:18 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
When would you be able to make the examples available?
Thanks!
Jack Anonymous

12/02/2013

04:28 PM FPGA Development: RE: FPG DDR3 Memory Pin Assignment

Hi Dan,
We would like to use the HPS DDR as well, but as you can see from my numerous posts, we are really stuck o... Anonymous

04:17 PM FPGA Development: RE: FPG DDR3 Memory Pin Assignment

Hi Jack,
Hmm, are you using the DDR SDRAM Controller with UniPHY in your QSYS project?
Also with this first rel... Daniel Vincelette

02:34 PM FPGA Development: RE: FPG DDR3 Memory Pin Assignment

Hi Dan,
I don't see the TCL file that you are referring to. All the tcl files that I have are for HPS DDR not FPGA... Anonymous

02:30 PM FPGA Development: RE: FPG DDR3 Memory Pin Assignment

Hi Jack,
Did you also run the IO Standard TCL file generated by the tools?
Dan Daniel Vincelette

02:25 PM FPGA Development: RE: FPG DDR3 Memory Pin Assignment

Hi Dan,
I ran the tcl script that you attached on this thread.
But when I tried to compile, it gives me errors ... Anonymous

02:21 PM FPGA Development: RE: FPG DDR3 Memory Pin Assignment

Hi Jack,
The IO Standard TCL file should be auto-generated by the tools.
To run it from Quartus:
1) Go to Tool... Daniel Vincelette

12:32 PM FPGA Development: RE: FPG DDR3 Memory Pin Assignment

Hi Dan,
Could you provide the TCL file for the IO Standard as well please?
Thanks!
Jack Anonymous

10:52 AM FPGA Development: RE: FPG DDR3 Memory Pin Assignment

Hi Jack,
I have attached a TCL file that will setup the pin assignments for the FPGA DDR.
Dan Daniel Vincelette

11:31 AM FPGA Development: RE: Link Down

Hi Dan,
It happens while it's idling and booting up.
Thanks!
Jack Anonymous

11:05 AM FPGA Development: RE: Link Down

Hi Jack,
Is this while the dev kit is just idling in linux? Or is this just during boot up?
Dan Daniel Vincelette

11:03 AM FPGA Development: RE: HPS Memory Controller

Hi Jack,
Have you taken the SDRAM FPGA port out of reset? The register is called hps.sdr.ctrlgrp.fpgaportrst, the ... Daniel Vincelette

11/28/2013

04:57 PM FPGA Development: FPG DDR3 Memory Pin Assignment

Hi,
Can you please provide the pin assignment for the optional FPGA DDR3 memory please?
Thanks!
Jack Anonymous

11/27/2013

05:07 PM FPGA Development: RE: HPS Memory Controller

I read through the section for the Cyclone V on the HPS-FPGA AXI and the manual for the SDRAM that we are using but I... Anonymous

11/26/2013

04:37 PM FPGA Development: RE: HPS Memory Controller

Hi,
Can someone please get back to me on this?
Thanks!
Jack Anonymous