Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

12/23/2013

10:46 AM FPGA Development: RE: I/O voltage

No problem, it can wait a while.
Sounds like the SOM may have been catered for. Any thoughts on the dev kit or do ... Nigel Doe

09:03 AM FPGA Development: RE: I/O voltage

Hi Nigel,
The best guy to answer this question is on break this week and a good chunk of next week, can you wait f... Michael Williamson

08:15 AM FPGA Development: I/O voltage

I would like to interface the MityARM-5C SX dev kit to an existing piece of equipment for evaluation purposes, howeve... Nigel Doe

12/16/2013

12:23 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
We figured it out last week. So we are fine with this for now.
Jack Anonymous

12/12/2013

05:17 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
I'm still confused about this. Would it be possible to provide an example of multiple packets?
For exam... Anonymous

12/10/2013

06:36 PM FPGA Development: RE: HPS Memory Controller

The descriptors are pushed onto a descriptor FIFO that the dispatcher reads from to start each transaction. So with s... Daniel Vincelette

05:18 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
Is there any timing diagram with the SGDMA? I want to control some of the signals directly in the FPGA.
... Anonymous

04:49 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
I'm confused about this, does the Go signal go to "0" after each transfer such that I have to toggle it ba... Anonymous

04:28 PM FPGA Development: RE: HPS Memory Controller

Yes, you need to set the go bit so the dispatcher knows that the descriptor is ready to be read.
Dan Daniel Vincelette

12:17 PM FPGA Development: RE: HPS Memory Controller

Hi again,
Just reading through the document. Do I have to set GO to '1' each time I update the descriptor?
Than... Anonymous

12:12 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
I'm changing the write address in the descriptor in the VHDL. But it's still only writing to the first add... Anonymous

12/09/2013

03:53 PM FPGA Development: RE: HPS Memory Controller

Hi Jack,
Park Writes – When set the dispatcher will continue to reissue the same descriptor to the write
master w... Daniel Vincelette

03:37 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
What's parked write? Is that just writing to one address only?
Is the descriptor like an address line?
... Anonymous

02:26 PM FPGA Development: RE: HPS Memory Controller

Hi Jack,
Each packet needs its own descriptor, unless you are using parked writes. The descriptor is what tells th... Daniel Vincelette

02:15 PM FPGA Development: RE: HPS Memory Controller

Hi,
Just a question with regarding sending these data as a package.
I know that the data in the package will be... Anonymous

12/06/2013

03:14 PM FPGA Development: RE: HSMC to GPIO

Hi Jack,
The 5CSX dev board follows the Altera defined pinout for HSMC so that should work.
Dan Daniel Vincelette

03:00 PM FPGA Development: HSMC to GPIO

Hi,
Is HSMC on base board laid out the same pin out as this particular Terasic daughter board (this is what Altera... Anonymous