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From 01/23/2014 to 02/21/2014

02:39 PM FPGA Development: RE: HPS Memory Controller: Nope, if you connect it to the HPS to FPGA bridge you can treat it more like a register that the code on the HPS read... Daniel Vincelette
01:10 PM FPGA Development: RE: HPS Memory Controller: Hi Dan,
Don't you mean connect it to the FPGA to HPS AXI bridge?
Our input data is processed in the FPGA.
Th... Anonymous
01:03 PM FPGA Development: RE: HPS Memory Controller: At that rate it might be simpler to create a FIFO in the FPGA and connect it to the light weight HPS to FPGA bridge. ... Daniel Vincelette

05:33 PM FPGA Development: RE: HPS Memory Controller: Also, I'm trying to by pass the SGDMA dispatcher and use the write master directly.
Jack Anonymous
05:32 PM FPGA Development: RE: HPS Memory Controller: Hi Dan,
Our data is coming in at about 40 MHz,
Jack Anonymous
04:57 PM FPGA Development: RE: HPS Memory Controller: Hi Jack,
Looking in the SGDMA dispatcher core user guide, it appears that if you use the extended descriptors you ... Daniel Vincelette
04:33 PM FPGA Development: RE: HPS Memory Controller: Hi Dan,
Regarding the SGDMA Write Master Core. I looked through the document for this core and it doesn't give any... Anonymous
03:40 PM FPGA Development: RE: HPS Memory Controller: Jack,
We do not currently have an example that uses a non-packetized Avalon stream. There should be an option in t... Daniel Vincelette
03:22 PM FPGA Development: RE: HPS Memory Controller: Hi,
Do you have any write to HPS memory examples where I can send data into the memory in a continuous stream rath... Anonymous

03:02 PM FPGA Development: RE: Signal Tap & JTAG FPGA Programming: Glad to hear you got it working.
Dan Daniel Vincelette
03:01 PM FPGA Development: RE: Signal Tap & JTAG FPGA Programming: Hi Dan,
Yes it works with the rbf file and it works when I program it in Linux. No problems there.
I managed to... Anonymous
01:58 PM FPGA Development: RE: Signal Tap & JTAG FPGA Programming: Hi Jack,
I've just created a wiki page for the steps that it takes to program the FPGA using the USB-Blaster, woul... Daniel Vincelette
12:58 PM FPGA Development: Signal Tap & JTAG FPGA Programming: Hi,
I'm raised the issue before regarding programming the FPGA with JTAG.
I have tried programming via JTAG, th... Anonymous

11:29 AM Software Development: Bitbake Error: I am running into the current error while running bitbake:
jliriano@ArmDev:~/yocto/build$ bitbake u-boot
ERROR: ... Julio Liriano

03:55 PM Software Development: Yocto Plug-In Python.exe Error: Posting on behalf of a customer:... Alexander Block

10:01 AM FPGA Development: RE: Ethernet: Edited my response. Good eye Dave. Thanks! Gregory Gluszek
09:31 AM FPGA Development: RE: Ethernet: Greg,
Only 2 "e"s in setenv, not three... Jack probably knows that, but just to be clear...
Dave
David Rice
09:10 AM FPGA Development: RE: Ethernet: Hi Jack,
Follow these steps to correct the ethernet:
1. Break into u-boot by resetting the system and hitting ... Gregory Gluszek

06:48 PM FPGA Development: RE: Ethernet Rev B: Hi,
I just received your rev B module. We noticed that the ethernet doesn't work on this revision at all. Is there... Anonymous

12:56 PM FPGA Development: RE: Load FPGA Timeout Error: Hi Jack,
I'm not sure what else to try other than trying to program the FPGA through a JTAG pod, which I believe y... Daniel Vincelette

01:57 PM FPGA Development: RE: Load FPGA Timeout Error: Hi Dan,
I did what Adam suggested and it made no difference. I tried it without anything plugged in and still noth... Anonymous
01:21 PM FPGA Development: RE: Load FPGA Timeout Error: Currently I do not believe that is the case, seeing as this problem is happening in both uboot and linux.
Have you... Daniel Vincelette
12:28 PM FPGA Development: RE: Load FPGA Timeout Error: Could this be a OS issue that's causing it?
Can some one direct me the exact link where I can download the img fil... Anonymous

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