Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

02/22/2014

07:48 AM Software Development: RE: Yocto Plug-In Python.exe Error

Can you post a capture of your complete shell interaction? Michael Williamson

02/20/2014

02:39 PM FPGA Development: RE: HPS Memory Controller

Nope, if you connect it to the HPS to FPGA bridge you can treat it more like a register that the code on the HPS read... Daniel Vincelette

01:10 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
Don't you mean connect it to the FPGA to HPS AXI bridge?
Our input data is processed in the FPGA.
Th... Anonymous

01:03 PM FPGA Development: RE: HPS Memory Controller

At that rate it might be simpler to create a FIFO in the FPGA and connect it to the light weight HPS to FPGA bridge. ... Daniel Vincelette

02/19/2014

05:33 PM FPGA Development: RE: HPS Memory Controller

Also, I'm trying to by pass the SGDMA dispatcher and use the write master directly.
Jack Anonymous

05:32 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
Our data is coming in at about 40 MHz,
Jack Anonymous

04:57 PM FPGA Development: RE: HPS Memory Controller

Hi Jack,
Looking in the SGDMA dispatcher core user guide, it appears that if you use the extended descriptors you ... Daniel Vincelette

04:33 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
Regarding the SGDMA Write Master Core. I looked through the document for this core and it doesn't give any... Anonymous

03:40 PM FPGA Development: RE: HPS Memory Controller

Jack,
We do not currently have an example that uses a non-packetized Avalon stream. There should be an option in t... Daniel Vincelette

03:22 PM FPGA Development: RE: HPS Memory Controller

Hi,
Do you have any write to HPS memory examples where I can send data into the memory in a continuous stream rath... Anonymous

02/13/2014

03:02 PM FPGA Development: RE: Signal Tap & JTAG FPGA Programming

Glad to hear you got it working.
Dan Daniel Vincelette

03:01 PM FPGA Development: RE: Signal Tap & JTAG FPGA Programming

Hi Dan,
Yes it works with the rbf file and it works when I program it in Linux. No problems there.
I managed to... Anonymous

01:58 PM FPGA Development: RE: Signal Tap & JTAG FPGA Programming

Hi Jack,
I've just created a wiki page for the steps that it takes to program the FPGA using the USB-Blaster, woul... Daniel Vincelette

12:58 PM FPGA Development: Signal Tap & JTAG FPGA Programming

Hi,
I'm raised the issue before regarding programming the FPGA with JTAG.
I have tried programming via JTAG, th... Anonymous

02/07/2014

11:29 AM Software Development: Bitbake Error

I am running into the current error while running bitbake:
jliriano@ArmDev:~/yocto/build$ bitbake u-boot
ERROR: ... Julio Liriano

02/03/2014

03:55 PM Software Development: Yocto Plug-In Python.exe Error

Posting on behalf of a customer:... Alexander Block

01/30/2014

10:01 AM FPGA Development: RE: Ethernet

Edited my response. Good eye Dave. Thanks! Gregory Gluszek

09:31 AM FPGA Development: RE: Ethernet

Greg,
Only 2 "e"s in setenv, not three... Jack probably knows that, but just to be clear...
Dave
David Rice

09:10 AM FPGA Development: RE: Ethernet

Hi Jack,
Follow these steps to correct the ethernet:
1. Break into u-boot by resetting the system and hitting ... Gregory Gluszek

01/29/2014

06:48 PM FPGA Development: RE: Ethernet Rev B

Hi,
I just received your rev B module. We noticed that the ethernet doesn't work on this revision at all. Is there... Anonymous

01/27/2014

12:56 PM FPGA Development: RE: Load FPGA Timeout Error

Hi Jack,
I'm not sure what else to try other than trying to program the FPGA through a JTAG pod, which I believe y... Daniel Vincelette