Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

03/05/2014

05:24 PM Software Development: RE: Reading memory into a file

Hi Jack,
It may take us some time to get to the bottom of this. We'll post in this thread as soon as we have addi... Gregory Gluszek

12:51 PM Software Development: RE: Reading memory into a file

Any update on this?? Anonymous

03/03/2014

05:59 PM Software Development: RE: Reading memory into a file

Hi Greg,
I have no problem with the software wihtout first sending the command to enable the SDRAM. The data that ... Anonymous

05:56 PM Software Development: RE: Reading memory into a file

Hi Jack,
Do you run into any problems if you use your software without first sending the command to enable the SD... Gregory Gluszek

03:45 PM Software Development: RE: Reading memory into a file

Hi,
I managed to read memory into a file but we got another problem.
We are following your example - write to h... Anonymous

02/27/2014

02:40 PM Software Development: RE: Reading memory into a file

Jack,
We don't have any general examples to provide.
If you're trying to share data over FTP or ssh in a human... Bob Duke

02:21 PM Software Development: Reading memory into a file

Hi,
Do you have any examples on reading memory in software?
We need to grab the data we have in memory into a f... Anonymous

02/22/2014

07:48 AM Software Development: RE: Yocto Plug-In Python.exe Error

Can you post a capture of your complete shell interaction? Michael Williamson

02/20/2014

02:39 PM FPGA Development: RE: HPS Memory Controller

Nope, if you connect it to the HPS to FPGA bridge you can treat it more like a register that the code on the HPS read... Daniel Vincelette

01:10 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
Don't you mean connect it to the FPGA to HPS AXI bridge?
Our input data is processed in the FPGA.
Th... Anonymous

01:03 PM FPGA Development: RE: HPS Memory Controller

At that rate it might be simpler to create a FIFO in the FPGA and connect it to the light weight HPS to FPGA bridge. ... Daniel Vincelette

02/19/2014

05:33 PM FPGA Development: RE: HPS Memory Controller

Also, I'm trying to by pass the SGDMA dispatcher and use the write master directly.
Jack Anonymous

05:32 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
Our data is coming in at about 40 MHz,
Jack Anonymous

04:57 PM FPGA Development: RE: HPS Memory Controller

Hi Jack,
Looking in the SGDMA dispatcher core user guide, it appears that if you use the extended descriptors you ... Daniel Vincelette

04:33 PM FPGA Development: RE: HPS Memory Controller

Hi Dan,
Regarding the SGDMA Write Master Core. I looked through the document for this core and it doesn't give any... Anonymous

03:40 PM FPGA Development: RE: HPS Memory Controller

Jack,
We do not currently have an example that uses a non-packetized Avalon stream. There should be an option in t... Daniel Vincelette

03:22 PM FPGA Development: RE: HPS Memory Controller

Hi,
Do you have any write to HPS memory examples where I can send data into the memory in a continuous stream rath... Anonymous

02/13/2014

03:02 PM FPGA Development: RE: Signal Tap & JTAG FPGA Programming

Glad to hear you got it working.
Dan Daniel Vincelette

03:01 PM FPGA Development: RE: Signal Tap & JTAG FPGA Programming

Hi Dan,
Yes it works with the rbf file and it works when I program it in Linux. No problems there.
I managed to... Anonymous

01:58 PM FPGA Development: RE: Signal Tap & JTAG FPGA Programming

Hi Jack,
I've just created a wiki page for the steps that it takes to program the FPGA using the USB-Blaster, woul... Daniel Vincelette

12:58 PM FPGA Development: Signal Tap & JTAG FPGA Programming

Hi,
I'm raised the issue before regarding programming the FPGA with JTAG.
I have tried programming via JTAG, th... Anonymous