Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

07/25/2014

02:42 PM Software Development: RE: PCI-e Device Driver - munmap related error

Can you post your code? Are you getting user space faults and not kernel oops, right?
Are you unmapping with the ... Michael Williamson

01:52 PM Software Development: PCI-e Device Driver - munmap related error

Posting on behalf of a customer:
I'm having some sporadic problems with the device driver I made for our pci-e dev... Alexander Block

07/24/2014

09:05 AM FPGA Development: RE: FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR)

Hi Nigel,
I don't believe there is a way to do it directly in QSYS. You may be able to patch your generated outpu... Adam Dziedzic

07:59 AM FPGA Development: RE: FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR)

Hi Adam,
Thanks for the insights.
Do you know how to persuade qsys to run the DDR at a slower speed? In normal ... Nigel Doe

07/23/2014

04:19 PM FPGA Development: RE: FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR)

Hi Nigel,
You are correct, the C8ES devices do not meet timing with the FPGA DDR according to Quartus. The ES sil... Adam Dziedzic

01:27 PM FPGA Development: FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR)

Although your reference design using FPGA DDR compiles as supplied, when I select the correct device (5CSXFC6C6U23C8E... Nigel Doe

07/21/2014

04:31 PM Software Development: Miscellaneous questions

Hi,
I'm using the pre-dev MitySOM eval board and I'm trying to rebuild a complete working environment with the cu... Pierre-Yves BRETECHER

07/20/2014

09:58 AM Software Development: Standard USB peripheral connection on MitySOM eval Board

Hi,
I originally wanted to connect to the board either usb storage peripherals or webcams-like peripherals. I bou... Pierre-Yves BRETECHER

07/17/2014

05:08 PM Software Development: RE: Pre production (-X) modules with newer sd image

That update to the conf/local.conf should fix the uImage issue. As for the building of the DTB through yocto, we push... Daniel Vincelette

03:42 PM Software Development: RE: Pre production (-X) modules with newer sd image

Thanks a lot for the feedback.
I have noticed that the Yocto wiki has just been updated concerning the uimage format... Pierre-Yves BRETECHER

09:13 AM Software Development: RE: Pre production (-X) modules with newer sd image

I am currently working through the kit and having a similar experience. The following seems to work for me in regard ... Nigel Doe

07/15/2014

06:28 PM Software Development: RE: Pre production (-X) modules with newer sd image

Well, the orange LED switches OFF because with this new version of the SD card, the FPGA is loaded with a firmware at... Pierre-Yves BRETECHER

07/11/2014

09:34 AM Software Development: RE: Building u-Boot and Preloader

I believe that the files in question need to be copied from software/spl_bsp/generated into u-boot-socfpga/board/cl/m... Nigel Doe

07/10/2014

02:23 PM Software Development: RE: Breaking changes on early MityARM

Should have spotted that note but somehow managed to miss it!
Thanks,
Nigel. Nigel Doe

02:00 PM Software Development: RE: Breaking changes on early MityARM

Hello Nigel,
Sorry about that. The description of the hardware changes for the Dev Kit baseboard are here:
htt... Michael Williamson

01:49 PM Software Development: Breaking changes on early MityARM

I have an early MityARM module and dev kit. On trying to implement the latest software versions I found that the Ethe... Nigel Doe

08:42 AM Software Development: Building u-Boot and Preloader

I am just revisiting the development kit after working on other projects and I am trying to locate the copy_files.sh ... Nigel Doe

07/08/2014

12:17 PM Software Development: Pre production (-X) modules with newer sd image

Hi,
I'am just starting to discover the eval kit. The one I ordered from Mouser was a pre-prod (- X) version. I und... Pierre-Yves BRETECHER

07/07/2014

07:22 AM Software Development: Sample c program to read/write Cyclone V FPGA internal memory through hps2fpga bridge

Hi,
Do you have sample c/c++ program to read/write a memory inside Cyclone V FPGA through hps2fpga bridge interfac... Bill Lee

07/03/2014

05:14 PM FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol

Hi Bill,
Sorry for the confusion. The latest image updated the Baud Rate to 115.2kbps to be consistent with the r... Adam Dziedzic

05:05 PM FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol

Hi,
I downloaded the sd_image_mitysom_5csx_rev1B.zip, and extracted out the .bin file. Then I typed "sudo dd if=sd... Bill Lee

07/02/2014

09:27 PM FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol

Information on how to make an SD card based upon the current Development Kit SD card image (Rev 1B) can be found on t... Alexander Block

06:17 PM FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol

Mike,
I think you meant "memtool -32 0xFFD0501C=0x06" for brgmodrst register. The reset value of the register some... Bill Lee

08:52 AM FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol

For reference on the reset register:
http://www.altera.com/literature/hb/cyclone-v/hps.html#reg_default_component/... Michael Williamson

08:51 AM FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol

Hi Bill,
It looks like you are using version 3.8 of the kernel. Version 3.8 does not have the FPGA bridge drivers... Michael Williamson

06/27/2014

09:52 PM FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol

Hi Mike,
I attached 2 files as you indicated in your previous reply. One is boot.log and another one is foo.txt.
... Bill Lee

07:56 AM FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol

If you can't see the enable file then the driver for the device isn't compiled in or the device tree blob doesn't ins... Michael Williamson