Activity
From 05/21/2017 to 06/19/2017
06/14/2017
- Hello, I have a 5CSX-H6-4YA-RI board.
What do I pull the MSEL lines up to when I pull them up.
(what is VCCPGM p...
06/07/2017
- 02:20 PM Software Development: RE: Using EEPROM available on MitySOM-5CSX
- Hello Mike and Adam,
I very much appreciate you both providing other suggestions readily available with our MitySO...
06/02/2017
- 12:14 PM Software Development: RE: Using EEPROM available on MitySOM-5CSX
- The QSPI NOR is supported by the MTD layer, so you should be able to partition it and mount it using JFFS2 (or perhap...
- 12:05 PM Software Development: RE: Using EEPROM available on MitySOM-5CSX
- We're using the 5CSX-H6-4YA so we should have 32MB of QSPI NOR, and we are booting from SD card, though it's possible...
- 10:25 AM Software Development: RE: Using EEPROM available on MitySOM-5CSX
- Hi Jared,
If you are looking for a small amount of space, there is also some memory available in the RTC. There i...
06/01/2017
- 11:52 PM Software Development: RE: Using EEPROM available on MitySOM-5CSX
- Hi Jared,
Before you get into the I2C EEPROM, does the MitySOM you are using have the QSPI NOR FLASH installed (mo... - +Context:+
My team would like to store some non-volatile data specific to a unit of hardware (independent of the S...
05/23/2017
- 08:32 PM Software Development: RE: Altera spi
- Brian,
Glad to hear it! You're welcome
Dan - 06:24 PM Software Development: RE: Altera spi
- Dan,
Got it working. Thanks for all the help.
Brian - 06:12 PM Software Development: RE: Altera spi
- Brian,
It looks like the Altera GPIO documentation is wrong, in the the driver it's looking for GPIO interrupts to... - 05:57 PM Software Development: RE: Altera spi
- Dan,
I just tried this and I'm getting the same error. I posted my updated dts.
Thanks,
Brian - 05:55 PM Software Development: RE: Altera spi
- Dan,
I just tried this and I'm getting the same error. I posted my updated dts.
Thanks,
Brian - 05:28 PM Software Development: RE: Altera spi
- Brian,
I think this variable was changed to "altr,interrupt-trigger" in the newer kernel. Here is the documentatio... - 05:23 PM Software Development: RE: Altera spi
- Dan,
I have most of it working. The only problem I see now is the gpio not showing up. I'm getting the following err... - 02:38 PM Software Development: RE: Altera spi
- Brian,
Can you post your boot output?
I would recommend doing a diff of the DE0 nano board dts and that one. Th... - 08:21 PM Software Development: RE: Virtual SPI device setup and access using spidev - Altera Cyclone V case
- Glad to hear you got it to work!
Dan - 06:48 PM Software Development: RE: Virtual SPI device setup and access using spidev - Altera Cyclone V case
- Dan,
solved also this step!
I rebuilt the my kernel version using the default .config you suggested me, modified... - 05:20 PM Software Development: RE: Virtual SPI device setup and access using spidev - Altera Cyclone V case
- Glad to hear!
I used our mitysom5csx_devkit_defconfig that is part of our 3.16 kernel
kernel: https://support.c... - 05:04 PM Software Development: RE: Virtual SPI device setup and access using spidev - Altera Cyclone V case
- Dan,
thanks for it.
I've added the spi0 section at the bottom of my dts and it works!!! Fantastic!!
The only po... - 02:32 PM Software Development: RE: Virtual SPI device setup and access using spidev - Altera Cyclone V case
- Hello Gianni,
I see that you've tried to add both the spidev devices to a FPGA spi core and the HPS peripheral. I ...
05/22/2017
- 07:59 PM Software Development: RE: Altera spi
- Dan,
I compiled the rel_socfpga-4.1.33-ltsi-rt_17.05.01_pr branch of the kernel form altera open source. I replaced ...
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