Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

06/20/2017

05:59 PM FPGA Development: RE: Power fail interrup

Clyde,
Offhand our recommendation would be to utilize an HPS GPIO and have it configured in the GPIO controller as... Alexander Block

05:14 PM FPGA Development: RE: Power fail interrupt

What more is there to say, really? We have a low voltage supervisor in our design and when the power is going to fai... Clyde Shappee

04:45 PM FPGA Development: RE: Power fail interrup

Hello Clyde,
Could you describe the situation a bit more?
Thanks!
Dan Daniel Vincelette

02:05 PM FPGA Development: Power fail interrup

What is the recommended input to the SOM for a power fail interrupt?
clyde Clyde Shappee

06/14/2017

09:10 PM PCB Development: VCCPGM and VCCBAT

Hello, I have a 5CSX-H6-4YA-RI board.
What do I pull the MSEL lines up to when I pull them up.
(what is VCCPGM p... Craig Drennan

06/07/2017

02:20 PM Software Development: RE: Using EEPROM available on MitySOM-5CSX

Hello Mike and Adam,
I very much appreciate you both providing other suggestions readily available with our MitySO... Jared Kirschner