Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

07/18/2017

07:56 PM Software Development: RE: I2C Slave Communication Hanging

Some additional context / correction:
I2C2 and I2C3 are both configured the same way. If you replace "3" with "2" ... Jared Kirschner

07:33 PM Software Development: RE: I2C Slave Communication Hanging

All,
This is the open drain primitive we are using for the I2C interfaces:
wire w_i2c3_scl_oe, w_i2c3_scl, w_... Clyde Shappee

05:09 PM Software Development: RE: I2C Slave Communication Hanging

Are you using the open drain primitive in the top level of the FPGA project?
-Mike
Michael Williamson

05:00 PM Software Development: RE: I2C Slave Communication Hanging

I've attached the driver source/header. I'm waiting to hear from the touch controller vendor whether I can share the ... Jared Kirschner

04:50 PM Software Development: RE: I2C Slave Communication Hanging

We are using I2C2 routed through the FPGA fabric (see image "I2C2_Connector.PNG"). It does have pullups to the best o... Jared Kirschner

04:32 PM Software Development: RE: I2C Slave Communication Hanging

Also, Can you share a snippet of the user space code you are using to issue the read request?
Thanks.
-Mike
Michael Williamson

04:15 PM Software Development: RE: I2C Slave Communication Hanging

Which I2C bus are you using? An HPS peripheral connected directly to HPS pins or routed via FPGA fabric?
This alm... Michael Williamson

02:52 PM Software Development: I2C Slave Communication Hanging

We're experiencing a problem with I2C communications with a slave on address 0x55 on a MitySOM-5CSX, shown in the att... Jared Kirschner

07/13/2017

03:29 PM FPGA Development: RE: I2C Controller

Thank you, this was resolved, turned out to be a problem with our build scripts. Harrison Barclay

07/12/2017

12:06 PM FPGA Development: RE: I2C Controller

Harrison
Whenever you change anything to do with HPS pin assignments, you will need to rebuild the preloader and upd... Tim Iskander

07/11/2017

05:51 PM FPGA Development: I2C Controller

Hello,
Unsure whether to post this under the software or FPGA topic.
We are transitioning from a mostly working... Harrison Barclay

07/04/2017

03:13 PM Software Development: RE: Accessing NOR flash from Linux on 5CSX

We have a wiki page relating to using the quad spi NOR [primarily centered around booting from NOR]
(https://suppor... Tim Iskander

08:10 AM Software Development: RE: Accessing NOR flash from Linux on 5CSX

Thanks Tim, that's good news.
Is there any specific doc. for the 5CSZ build? e.g. driver name, build instructio... Bruce Kenny

07/03/2017

05:22 PM Software Development: RE: Accessing NOR flash from Linux on 5CSX

Bruce
Linux has excellent support for NOR flash devices using the mtd subsytem
http://www.linux-mtd.infradead.org/
... Tim Iskander

04:53 PM Software Development: Accessing NOR flash from Linux on 5CSX

Our project is currently in the design phase and we are considering using a small amount of NOR flash to read and wri... Bruce Kenny

06/20/2017

05:59 PM FPGA Development: RE: Power fail interrup

Clyde,
Offhand our recommendation would be to utilize an HPS GPIO and have it configured in the GPIO controller as... Alexander Block

05:14 PM FPGA Development: RE: Power fail interrupt

What more is there to say, really? We have a low voltage supervisor in our design and when the power is going to fai... Clyde Shappee

04:45 PM FPGA Development: RE: Power fail interrup

Hello Clyde,
Could you describe the situation a bit more?
Thanks!
Dan Daniel Vincelette

02:05 PM FPGA Development: Power fail interrup

What is the recommended input to the SOM for a power fail interrupt?
clyde Clyde Shappee