Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

03/27/2019

09:53 AM FPGA Development: RE: Problem when programming FPGA from HPS

I attach the simple block diagram-based Quartus project that takes in input a 100 MHz differential clock and outputs ... Davide Vaccaro

03/26/2019

05:23 PM FPGA Development: RE: Problem when programming FPGA from HPS

Can attach a copy of your reference project? Is it based off of the one on our support site?
-Mike Michael Williamson

04:55 PM FPGA Development: RE: Problem when programming FPGA from HPS

So, I tried all the methods listed in https://rocketboards.org/foswiki/view/Documentation/GSRD131ProgrammingFPGA, but... Davide Vaccaro

03/25/2019

03:11 PM FPGA Development: RE: Problem when programming FPGA from HPS

Hi Mike,
in the "final" Quartus program I will indeed need to change the configurations you mentioned, but for a s... Davide Vaccaro

03/20/2019

04:58 AM Software Development: Dual QSPIs + Device Tree

I've got a SOM with 2 QSPIs. I'd like to be able to access both in Linux. Does anyone have an example of a .dts file ... Shane Avery

03/19/2019

03:40 PM FPGA Development: RE: Problem when programming FPGA from HPS

Hi Davide,
Are you enabling or changing the configuration of the FPGA to SDRAM (fpga2sdram) or HPS AXI crossbars i... Michael Williamson

03:25 PM FPGA Development: Problem when programming FPGA from HPS

Hi everyone,
I looked at previous posts but the solutions outlined does not seem to work in my case, so I'm writin... Davide Vaccaro