Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

11/21/2023

04:59 PM PCB Development: RE: Pin connection

Hello Dan,
Thanks for providing this information and support. According to this datasheet, the FPGA module has an... Mohammad Hassan Adeli

11/20/2023

06:30 PM PCB Development: RE: Pin connection

Hello Mohammad,
Please take a look at our development board schematic, if you haven't already. It can be found her... Daniel Vincelette

11/17/2023

07:38 PM PCB Development: RE: Pin connection

Thanks for your reply, Mike. I used Y13 as the clock pin in the development board and I wonder where internally in th... Mohammad Hassan Adeli

07:30 PM PCB Development: RE: Pin connection

Hi Mohammad,
If you open up the Datasheet and check Table 8 and search for Y13 you should that it is a direct conn... Michael Williamson

07:08 PM PCB Development: Pin connection

Hello,
I have a development kit of MitySOM-5csx (https://www.criticallink.com/product/mitysom-5csx-dev-kit/). I w... Mohammad Hassan Adeli

11/16/2023

06:18 PM MitySOM-5CSX Embedded Vision Developer's Kit for Basler dart BCON Support: RE: Barrel jack type

Marko,
The manufacturer part number used for the barrel jack is PJ-059BH. I have attached the manufacturer datashe... Alexander Block

07:28 AM MitySOM-5CSX Embedded Vision Developer's Kit for Basler dart BCON Support: Barrel jack type

Hello,
I was wondering if you could help me find information on the specifications for the barrel plug, we need t... Marko Mamić

03:02 PM FPGA Development: Clock frequency pins

Hello,
We have this module (https://www.criticallink.com/product/mitysom-5csx/ ) board on our project board and al... Mohammad Hassan Adeli

11/02/2023

02:35 AM PCB Development: RE: MSEL[4] and return current cap...

Sorry if I wasn't clear. The caps are optional. They might help in a worst case situation, but for most designs the... David Rice

11/01/2023

11:34 PM PCB Development: RE: MSEL[4] and return current cap...

Hi David,
I understand that, but the eval board only has them on MSEL[3:0] and does not have one on MSEL[4].  So, ... Austin Franklin

07:38 PM PCB Development: RE: MSEL[4] and return current cap...

The intention of the caps to ground on these signals is to allow some high frequency ground currents from the SOM I/O... David Rice

10/28/2023

06:54 PM PCB Development: MSEL[4] and return current cap...

The dev board has MSEL[3:0] with 1000pF caps, and MSEL[4] does not have a cap, unless I missed it. In the design gui... Austin Franklin

10/27/2023

06:10 PM FPGA Development: RE: Link missing on System Design Overview wiki page

Thank you for bringing this to our attention, I've updated the text on that wiki page so it now links to our referenc... Daniel Vincelette

10/26/2023

08:00 PM Software Development: RE: How to boot FPGA from U-Boot without having the uboot.env file in my SD card

Hi everyone,
For anyone who is reading, I have figured it out and I hope this will help you.
The U-Boot is runnin... Shahad Alrawi

02:24 AM FPGA Development: Link missing on System Design Overview wiki page

(posted on behalf of a customer)
on this URL:
https://support.criticallink.com/redmine/projects/mityarm-5cs/wik... Thomas Catalino