Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

07/25/2024

GG 07:47 PM Software Development: RE: how to access gpio using pio ip core in c code

Hello,
I would look at the avalon memory mapped slave address in your signal tap. It's possible the hps is requesting a read from a different address for one of those two cycles. It's also possible two reads are queued up back to bac... Gregory Gluszek

07/24/2024

BK 07:11 AM Software Development: RE: how to access gpio using pio ip core in c code

Hi,
Yes, I am verified in Signal Tap only. and as off now like, we are able to do read and write HPS to FPGA using LW_AVALON_MM interface. In case of read from HPS, avalon_slave_read signal is being high for two clock cycles. Where as... Bhardwaj Kotha

07/23/2024

GG 04:12 PM Software Development: RE: how to access gpio using pio ip core in c code

It looks like you posted a couple different versions of your C code. Which one are you running and what does the output look like? How are you verifying the FPGA is receiving data from the HPS? Are you using signal tap?
Thanks,
Greg Gregory Gluszek

07/22/2024

BK 03:16 PM Software Development: RE: how to access gpio using pio ip core in c code

Hi,
In my implementation, the Avalon Memory Mapped interface automatically assigned a base address in platform designer with that address only I successfully sent an 32bit incremental data from the HPS to the FPGA and received it corr... Bhardwaj Kotha

07/19/2024

DV 02:11 PM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

Hello,
For the reference project the makefile removes those lines from the sdc file before it does the build, if you aren't using the Makefile for doing the build then you need to manually delete those lines after running Platform Des... Daniel Vincelette

BK 06:45 AM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

Hi,
Yeah, I am removed that two lines in dev_5cs/synthesis/submodules/dev_5cs_hps_0_fpga_interfaces.sdc, before updating this one i am getting 30-40% of packet loss in ping , as off now I am updated that one now i am getting 5-7% of ... Bhardwaj Kotha

07/16/2024

DV 07:40 PM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

Hello,
I have verified that the reference design does meet timing when built via the makefile (ie make rbf). The makefile removes 2 incorrectly autogenerated clock assignments for the MAC clocks. The following lines need to be deleted... Daniel Vincelette

07/15/2024

GG 06:58 PM Software Development: RE: how to access gpio using pio ip core in c code

The most straightforward way to do that would be to create your own Platform Designer Component with an Avalon Memory Mapped Slave interface. (See https://www.intel.com/content/www/us/en/docs/programmable/683364/18-1/creating-components.... Gregory Gluszek

07/13/2024

BK 03:16 PM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

Hi,
with the provided reference project there is no packet loss but there are timing errors (screenshots attached) even after modified the reference project, as we said in first query, we observed similar timing errors with the same h... Bhardwaj Kotha

07/11/2024

DV 01:39 PM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

It sounds like you are on edge for timing so please verify that your design meets timing via TimeQuest in Quartus. Also when you used the provided reference project you did not see this packet lose, correct?
Dan Daniel Vincelette

BK 12:05 PM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

i had made HPS and emac Splitter Conduit signals to external in Platform Designer and I had assigned that conduit signals properly in top Module accordingly like, hps_0_emac0_phy_txd_o to rgmiib_emac_phy_txd_o and for that reference, ple... Bhardwaj Kotha

07/10/2024

DV 01:08 PM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

Hello,
For the case that you are seeing 60% packet lose, what did you change in the reference FPGA project that was supplied in the bnet_mps project? Also have you verified that your project is meeting timing?
Best regards,
Dan
Daniel Vincelette

BK 12:07 PM Software Development: RE: how to access gpio using pio ip core in c code

Yes, I wanted to send the 256 BITS of raw data from HPS to FPGA. Can you give me the supplies for that. Bhardwaj Kotha

07/08/2024

TI 03:09 PM Software Development: RE: Get URL from jenkins file

I just did a clean pull of the kernel and built it using the poky 3.0.4 sdk with no issues.
It sounds like either there was some old/other config in the build tree or your environment is different
my build did _not_ attempt to build th... Tim Iskander

GG 01:20 PM Software Development: RE: How to access gpio using c code in yocto linux, which is created using PIO IP with HPS

This seems to be a duplicate of https://support.criticallink.com/redmine/boards/45/topics/6705. Please refer to the other linked topic for further details.
Thanks,
Greg Gregory Gluszek

GG 01:18 PM Software Development: RE: how to access gpio using pio ip core in c code

Hello,
Can you share capture of your console so we can evaluate what commands you are using and exactly what errors are being reported?
As long as you do not exceed resources on the FPGA you should be able to add the required pio ... Gregory Gluszek

07/07/2024

BK 01:01 PM Software Development: RE: Get URL from jenkins file

Hi,
I have downloaded the kernel from https://git.criticallink.com/gitweb/?p=linux-socfpga.git;a=shortlog;h=refs/heads/socfpga-5.4.23-lts (branch socfpga-5.4.23-lts) and updated the device tree and defconfig files by taking them fr... Bhardwaj Kotha

07/05/2024

BK 08:53 AM Software Development: How to access gpio using c code in yocto linux, which is created using PIO IP with HPS

Hi,
I have added pio ip (output only) to the HPS block design in platform designer, and modified/added gpio block with address specification by converting the dtb file to dts. Again compiled back to new dtb and replaced in pre built os ... Bhardwaj Kotha

BK 08:51 AM Software Development: how to access gpio using pio ip core in c code

Hi,
I have added pio ip (output only) to the HPS block design in platform designer, and modified/added gpio block with address specification by converting the dtb file to dts. Again compiled back to new dtb and replaced in pre built ... Bhardwaj Kotha

07/04/2024

BK 07:34 AM Software Development: RE: Error in u-boot. cyclone v 5CSEBA4U2317 SOM

Hi Daniel,
Now am able to generate the boot files.
Thanks & Regards,
Bhardwaj Bhardwaj Kotha

BK 07:02 AM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

Hi,
I donot have much resources, as my application need more resources, I wanted to use HPS EMAC. And I am not going to implement any other IP layers, I just modify the data part and forward on the other port. For this, I have made emac... Bhardwaj Kotha

07/01/2024

DV 06:18 PM Software Development: RE: Error in u-boot. cyclone v 5CSEBA4U2317 SOM

Hello,
You shouldn't need to update the compiler or path from the default that are filled out by the bsp-editor. Did you also run into errors when you used the default cross compiler that was choosen by the bsp-editor?
Best regards... Daniel Vincelette

06/30/2024

TI 05:51 PM Software Development: RE: Get URL from jenkins file

Here is a link to the SDK for the 5CSx
you will need to run it on a linux machine (ubuntu 18 and up recommended)
https://support.criticallink.com/files/socfpga/poky-glibc-i686-epstech-image-bnet-mps-cortexa9hf-neon-mitysom-c5-toolchain... Tim Iskander

06/29/2024

BK 04:42 AM Software Development: RE: Error in u-boot. cyclone v 5CSEBA4U2317 SOM

Hi Daniel,
Thank you for providing the information regarding booting. I understand the process to boot the cyclone v board.
I had followed the process which is mentioned in [[https://support.criticallink.com/redmine/projects... Bhardwaj Kotha

06/28/2024

TI 03:59 PM Software Development: RE: Get URL from jenkins file

If you just need to build the kernel and device tree, you can download the kernel from https://git.criticallink.com/gitweb/?p=linux-socfpga.git;a=shortlog;h=refs/heads/socfpga-5.4.23-lts (branch socfpga-5.4.23-lts is what we used for the... Tim Iskander

DV 01:34 PM Software Development: RE: Error in u-boot. cyclone v 5CSEBA4U2317 SOM

Hello,
The Altera Cyclone V SoC boot process involves several steps to initialize and start up the system. The Cyclone V SoC integrates an ARM-based Hard Processor System (HPS) with FPGA fabric, and the boot process encompasses both t... Daniel Vincelette

06/27/2024

BK 05:36 PM Software Development: RE: Error in u-boot. cyclone v 5CSEBA4U2317 SOM

Hi Daniel,
I had the tested the booting by the link which you have mentioned. It is working but getting an error related to ethernet but the board is booted.
Is any FPGA code mandatory to boot the hps?
Can we boot the hps without ... Bhardwaj Kotha

BK 08:21 AM Software Development: RE: Get URL from jenkins file

Hi,
We need to build the project from provided jenkins file, and further we are going to modify or add avalon interface to communicated HPS and PL fabric, so we need to regenerate the device tree and build some software on top of it... Bhardwaj Kotha

06/26/2024

DV 06:48 PM Software Development: RE: Get URL from jenkins file

Hello,
I believe the Jenkins file you are referring to was provided as a reference and contains internal links to repositories at Critical Link. These links will need to be replaced with the repositories you will be hosting. Are you t... Daniel Vincelette

BK 05:31 PM Software Development: Get URL from jenkins file

Hi,
we have an Jenkins file, but we are new to Jenkins and i am not able to get URL from the Jenkins file. Help me out to get the that link and can you guide me the usage and Procedure of Jenkins
Thanking you,
Bhardwaj Kotha. Bhardwaj Kotha