Activity
From 06/27/2024 to 07/26/2024
07/25/2024
- 07:47 PM Software Development: RE: how to access gpio using pio ip core in c code
- Hello,
I would look at the avalon memory mapped slave address in your signal tap. It's possible the hps is reques...
07/24/2024
- 07:11 AM Software Development: RE: how to access gpio using pio ip core in c code
- Hi,
Yes, I am verified in Signal Tap only. and as off now like, we are able to do read and write HPS to FPGA using...
07/23/2024
- 04:12 PM Software Development: RE: how to access gpio using pio ip core in c code
- It looks like you posted a couple different versions of your C code. Which one are you running and what does the outp...
07/22/2024
- 03:16 PM Software Development: RE: how to access gpio using pio ip core in c code
- Hi,
In my implementation, the Avalon Memory Mapped interface automatically assigned a base address in platform des...
07/19/2024
- 02:11 PM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access
- Hello,
For the reference project the makefile removes those lines from the sdc file before it does the build, if y... - 06:45 AM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access
- Hi,
Yeah, I am removed that two lines in dev_5cs/synthesis/submodules/dev_5cs_hps_0_fpga_interfaces.sdc, before u...
07/16/2024
- 07:40 PM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access
- Hello,
I have verified that the reference design does meet timing when built via the makefile (ie make rbf). The m...
07/15/2024
- 06:58 PM Software Development: RE: how to access gpio using pio ip core in c code
- The most straightforward way to do that would be to create your own Platform Designer Component with an Avalon Memory...
07/13/2024
- 03:16 PM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access
- Hi,
with the provided reference project there is no packet loss but there are timing errors (screenshots attached)...
07/11/2024
- 01:39 PM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access
- It sounds like you are on edge for timing so please verify that your design meets timing via TimeQuest in Quartus. Al...
- 12:05 PM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access
- i had made HPS and emac Splitter Conduit signals to external in Platform Designer and I had assigned that conduit sig...
07/10/2024
- 01:08 PM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access
- Hello,
For the case that you are seeing 60% packet lose, what did you change in the reference FPGA project that wa... - 12:07 PM Software Development: RE: how to access gpio using pio ip core in c code
- Yes, I wanted to send the 256 BITS of raw data from HPS to FPGA. Can you give me the supplies for that.
07/08/2024
- 03:09 PM Software Development: RE: Get URL from jenkins file
- I just did a clean pull of the kernel and built it using the poky 3.0.4 sdk with no issues.
It sounds like either th... - 01:20 PM Software Development: RE: How to access gpio using c code in yocto linux, which is created using PIO IP with HPS
- This seems to be a duplicate of https://support.criticallink.com/redmine/boards/45/topics/6705. Please refer to the o...
- 01:18 PM Software Development: RE: how to access gpio using pio ip core in c code
- Hello,
Can you share capture of your console so we can evaluate what commands you are using and exactly what erro...
07/07/2024
- 01:01 PM Software Development: RE: Get URL from jenkins file
- Hi,
I have downloaded the kernel from https://git.criticallink.com/gitweb/?p=linux-socfpga.git;a=shortlog;h=refs...
07/05/2024
- Hi,
I have added pio ip (output only) to the HPS block design in platform designer, and modified/added gpio block wi... - Hi,
I have added pio ip (output only) to the HPS block design in platform designer, and modified/added gpio block...
07/04/2024
- 07:34 AM Software Development: RE: Error in u-boot. cyclone v 5CSEBA4U2317 SOM
- Hi Daniel,
Now am able to generate the boot files.
Thanks & Regards,
Bhardwaj - 07:02 AM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access
- Hi,
I donot have much resources, as my application need more resources, I wanted to use HPS EMAC. And I am not going...
07/01/2024
- 06:18 PM Software Development: RE: Error in u-boot. cyclone v 5CSEBA4U2317 SOM
- Hello,
You shouldn't need to update the compiler or path from the default that are filled out by the bsp-editor. D...
06/30/2024
- 05:51 PM Software Development: RE: Get URL from jenkins file
- Here is a link to the SDK for the 5CSx
you will need to run it on a linux machine (ubuntu 18 and up recommended)
ht...
06/29/2024
- 04:42 AM Software Development: RE: Error in u-boot. cyclone v 5CSEBA4U2317 SOM
- Hi Daniel,
Thank you for providing the information regarding booting. I understand the process to boot the...
06/28/2024
- 03:59 PM Software Development: RE: Get URL from jenkins file
- If you just need to build the kernel and device tree, you can download the kernel from https://git.criticallink.com/g...
- 01:34 PM Software Development: RE: Error in u-boot. cyclone v 5CSEBA4U2317 SOM
- Hello,
The Altera Cyclone V SoC boot process involves several steps to initialize and start up the system. The Cyc...
06/27/2024
- 05:36 PM Software Development: RE: Error in u-boot. cyclone v 5CSEBA4U2317 SOM
- Hi Daniel,
I had the tested the booting by the link which you have mentioned. It is working but getting an error ... - 08:21 AM Software Development: RE: Get URL from jenkins file
- Hi,
We need to build the project from provided jenkins file, and further we are going to modify or add avalon in...
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