Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

01/23/2025

TI 08:40 PM Software Development: RE: MTU increase Issue

What Dan showed you will start your application in the console... if your application exits (or you kill it with ctrl-c) you will be dropped to the command line, where you can restart your application or do other things. Tim Iskander

DV 06:55 PM Software Development: RE: MTU increase Issue

Hello,
As Tim said an application launched through cron won't have access to standard in and out. What you could do is have getty(the login manager) autologin as root and use a .profile config file to launch your application.
Here ... Daniel Vincelette

BK 03:17 PM Software Development: RE: MTU increase Issue

Hi,
I am currently working with the MitySOM Cyclone V device, which has only a single UART port. During boot-up, the boot logs are coming through this UART port. Once the system finishes booting, it prompts for a login. I am manually ... Bhardwaj Kotha

01/21/2025

TI 02:09 PM Software Development: RE: MTU increase Issue

If your program is reading from standard input, it will not be able to read anything when launched from cron. cron jobs have their standard input closed (or set to /dev/null, I don't remember exactly) and standard out will be shown in th... Tim Iskander

BK 01:03 PM Software Development: RE: Issue with crontab

Hi,
MTU size issue was Resolved, and now I am facing with Crontab.
Actually I am running an application code on boot time and that way I am added the Executable lines on crontab. I am facing an issue with that after booting, my code ... Bhardwaj Kotha

MW 01:43 PM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

The Quartus Platform designer adds logic between the AXI bridge (not sure which bridge you are using) and your Avalon Memory slave interfaces to account for the fact that the AXI interface is command / response vs. a more standard / typi... Michael Williamson

BK 01:18 PM FPGA Development: RE: MitySOM-5csx custom board Logic Utilization Issue

Hi,
I am working on Data transmission from HPS to FPGA fabric, So i am used Avalon Memory Interface in Platform Designer. The issue is when i am not using that Avalon Memory interface it takes 10974/15880(69%) Logic Utilization(in ALM... Bhardwaj Kotha