Project

General

Profile

Activity

From 02/09/2026 to 03/10/2026

02/23/2026

08:07 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
Hi Xiang,
Sorry about the delay. It looks like this is either due to a missing or unexpected character in the U-Bo...
Daniel Vincelette
07:03 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
Hi Dan,
Do you have any update, what I can do now?
BR,
Xiang
Xiang Shuai

02/09/2026

03:49 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
Hi Dan,

clipboard-202602091046-ikfkk.png
please see attached picture, that's a typo when I fill this page.
...
Xiang Shuai
 

Also available in: Atom

Go to top
Add picture from clipboard (Maximum size: 1 GB)