Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

02/27/2026

08:18 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout

Hi Xiang,
Are you using the "Makefile":https://support.criticallink.com/gitweb/?p=mitysom-5csx-ref.git;a=blob;f=de... Daniel Vincelette

07:07 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout

Hi Dan,
Thanks for your support, I build a envirment with Ubuntu 22.04 and Quartus 23.1; and finish re-build ub... Xiang Shuai

02/23/2026

08:07 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout

Hi Xiang,
Sorry about the delay. It looks like this is either due to a missing or unexpected character in the U-Bo... Daniel Vincelette

07:03 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout

Hi Dan,
Do you have any update, what I can do now?
BR,
Xiang Xiang Shuai