Activity
From 12/06/2013 to 01/04/2014
01/02/2014
- MW 08:14 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Regarding handling UART of MitydspL138 F
- Which UART are you after? Which processor core would you like to use with it?
- Dear sir,
It is given in MitydspL138F VDK datasheet that already UART driver is available in Kernel image. Can you provide more details regarding it as we wanted to use UART in interrupt mode.
with regards,
Naveen K.S. - MW 08:12 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: USB-OTG as a peripheral and a host
- Hello,
It looks like you have selected the "gadget zero" device as your peripheral device. This is a USB test device setup.
You need to go back to your kernel configuration deselect the gadget zero device and select the RNDIS devi...
12/31/2013
- Hello,
I am using a MityDSP L138F with a custom board. This board has provision for a USB 1.1 Host and an USB 2 OTG port. I am trying to configure the USB-OTG port as a peripheral and get it detected through a Windows as well as a Linux...
12/23/2013
- ND 10:46 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: I/O voltage
- No problem, it can wait a while.
Sounds like the SOM may have been catered for. Any thoughts on the dev kit or do you need to wait for the designer to get back?
Thanks.
Nigel. - MW 09:03 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: I/O voltage
- Hi Nigel,
The best guy to answer this question is on break this week and a good chunk of next week, can you wait for an answer?
Looking at the schematic, VCCPD3B4A is driven by a small compare/mux circuit that selects 2.5 V if VIO_... - I would like to interface the MityARM-5C SX dev kit to an existing piece of equipment for evaluation purposes, however this equipment uses 3.3v I/O. Is seems from the schematic that the bank I/O for the FPGA signals on the HSMC interface...
12/20/2013
- DR 11:46 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: DSP- EDMA Transmission problem
- I'm not sure why you are dividing by 4 for the number of words to transfer (numwords>>2), but I think that is your problem. ii will be set to 1024 in the example you show, so it should transfer 1024 16-bit words, which is what you are s...
- Hello,
I am having the following problem:
I am invoking an EDMA transfer in my DSP-side application. To do so, I did the following:
12/19/2013
- MW 07:16 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: "Regarding video Frame data flow without using Linux OS-Linux frame buffer"
- Hi Naveen,
You can use the UPP port (see the tcDspUpp core in the DSP/core library) or use the VPIF (same pins, see the tcDspVpif class) with the 674x core in DSP/BIOS to have the DSP receive data directly.
We only use / support Li... - Hello sir,
Thank you for replying my previous queries.
We are using MitydspL138F VDK for developing prototype, for one of our image processing application project. The complete Qt framework of the kit is explained fine in the VDK d...
12/16/2013
-
12:23 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: HPS Memory Controller
- Hi Dan,
We figured it out last week. So we are fine with this for now.
Jack - MW 09:50 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- And... the capacitance requirements for any USB interface are *very* important. See the USB specification (usb.org) on the capacitance and in-rush current requirements. If you don't get these right, you may have trouble getting the HOS...
- MW 09:48 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- Hello Helmut,
This is really an embedded linux question in general and not just a MityDSP-L138 specific question. But to get the OTG port to look like a mass storage device, you will need to enable the MASS STORAGE device gadget in ... - HF 09:36 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- Thanks. I'm tasking my kernel guy on this. The link for RNDIS advice will be helpful.
HOWEVER, I would prefer it look like a mass storage device, so the host PC can directly access the embedded system's file system.
But when I se...
12/14/2013
- MW 08:38 AM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: 24bit LCD and Wifi module
- Not using the Development kit. Those pins are needed for the MMC / SDIO interface for the Bluetooth device as the pinmux options are selected.
It may be possible on your own custom board. The expansion kit needs an MMC / SDIO interf...
12/13/2013
- MW 02:07 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Accessing SPI1 bus
- Hi,
To get the spidev device, you need to add an entry for it in your platform baseboard file.
See the recent "industrial I/O board platform file":http://support.criticallink.com/gitweb/?p=linux-davinci.git;a=blob;f=arch/arm/mach-d... - MF 01:40 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Accessing SPI1 bus
- Nope. I don't see that either.
I am going with the low level register access for now. I have SPI driver code that ran on a C6748 and am porting that. You can gain access to the registers using mmap(). - GG 12:21 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Accessing SPI1 bus
- Hi Mary,
My guess would be that since in your baseboard file you set the modalias to "M25PE80" as part of the spi_board_info you will get a /dev/M25PE801.1 entry, or something to that affect, instead of /dev/spidev1.1.
Thanks,
\Greg
12/12/2013
- MW 06:56 PM MityDSP (TI TMS320C6xxx Based Products) FPGA Development: RE: ASADSn / ASREn pin loc
- EMIF_ASADS# is routed to Y16, bank 4.
-Mike
- Hi,
Is the EMIFA signal ASADSn/ASREn routed to the FPGA? If so, what is the pin location?
I'm using the MityDSP-Pro, 6455-JE-3X5-R.
Cheers,
Leon Craven - LC 05:48 PM MityDSP (TI TMS320C6xxx Based Products) FPGA Development: RE: Additional Address Lines EA[19 downto 10] pin loc
- Thanks
- MW 05:47 PM MityDSP (TI TMS320C6xxx Based Products) FPGA Development: RE: Additional Address Lines EA[19 downto 10] pin loc
- Hi Leon,
Here are the rest of the EMIF_AEA pin assignments.
-Mike
| NET | FPGA PIN | FPGA BANK |
| EMIF_AEA10 | AA9 | 5 |
| EMIF_AEA11 | AC11 | 5 |
| EMIF_AEA12 | AE12 | 5 |
| EMIF_AEA13 | AC10 | 5 ... - LC 04:48 PM MityDSP (TI TMS320C6xxx Based Products) FPGA Development: RE: Additional Address Lines EA[19 downto 10] pin loc
- Hi,
Sorry, I'm using the MityDSP-Pro, 6455-JE-3X5-R.
Cheers,
Leon - MW 07:08 AM MityDSP (TI TMS320C6xxx Based Products) FPGA Development: RE: Additional Address Lines EA[19 downto 10] pin loc
- Hi Leon,
While module are you using? Do you have a model number or a part number?
-Mike
-
05:17 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: HPS Memory Controller
- Hi Dan,
I'm still confused about this. Would it be possible to provide an example of multiple packets?
For example two packets each with a counter.
Thanks!
Jack - Hi,
Is it possible to use GPMC_AD8 to GPMC_AD15 pins to drive 24bit LCD and install/run WiFi 802.11 b/g/n with Bluetooth Expansion Kit at the same time?
Andrey - MC 06:48 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Call to tcDspFpgaGpio::ConfigurePin() makes the Dsp crash
- Thanks Mike!
That was definitely the reason of the crash.
Thank you.
Michele
12/11/2013
- Hi,
In the supplied ucf files I can only find pin information for address lines i_emif_aea[9 downto 0]. I would like to use the other address lines. Are they routed to the FPGA? If so what are their pin locations on the FPGA.
Regar... - JC 04:01 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- The only things I see different in your circuit besides the removed 5V vbus switch(U101) are:
* Missing USB0_ID pulldown (R110)
* Missing capacitor (C119)
I'm not sure if either of these are required if using the port in periphera... - HF 12:17 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- Jonathan,
Yes, we have a USB A connector coming from USB 0. So this should be akin to connecting a USB A to USB mini cable from the PC to the system. So I *should* be able to get this work. But no, there is not 5V being provided. ... - JC 11:31 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- Mike, Correct me if I'm wrong.
"So maybe the question boils down to this. Can you plug a USB OTG device into a PC, using what kind of cable, and it all work itself out with the PC as host and the device as peripheral? If so, then I ne... - HF 11:03 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- Michael,
Great. First, the P/N on my Critical Link baseboard actually matches the next to last, "80-000268RI-2 B". But if I need to make a revision to the board, I'll consult the last entry as you advised.
(((Please humor me whil... - MW 07:28 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- Schematics for the industrial I/O base board are on this "wiki page":http://support.criticallink.com/redmine/projects/indio/wiki/Industrial_IO_Revision_Information. Use the most recent one.
There are 2 USB ports available. 1 only su... - HF 07:08 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- Jonathan, I'll try those things. FYI one test case with a USB flash drive works for the critical link baseboard, but not our custom baseboard. I need to compare schematics. There may be something different, such as failure to provide ...
- MW 07:12 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Call to tcDspFpgaGpio::ConfigurePin() makes the Dsp crash
- Hi Michele,
Set the CORE_INT_EOF_LEVEL to 1.
Our framework uses 2 levels (2 seperate GPIO interrupt lines between FPGA and OMAP-L138). By default, level 0 is used for cores managed by the ARM and level 1 is used for cores managed ... - MC 05:48 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Call to tcDspFpgaGpio::ConfigurePin() makes the Dsp crash
- This is the crash dump on the serial output:
Unable to handle kernel NULL pointer dereference at virtual address 00000000
pgd = c5368000
[00000000] *pgd=c5312831, *pte=00000000, *ppte=00000000
Internal error: Oops: 80000005 [#1] PR...
12/10/2013
- DG 09:27 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- Hello!
If you have got console why don't you just copy files from your PC to board?
And another option - if USB host is available on the board, just connect a USB stick and copy files from it.
Make sure that something like
/dev/mmcbl... - DV 06:36 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- The descriptors are pushed onto a descriptor FIFO that the dispatcher reads from to start each transaction. So with setting the go bit, the descriptor will be written on to this FIFO.
To send multiple packets you will have to push mul... -
05:18 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: HPS Memory Controller
- Hi Dan,
Is there any timing diagram with the SGDMA? I want to control some of the signals directly in the FPGA.
Thanks!
Jack -
04:49 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: HPS Memory Controller
- Hi Dan,
I'm confused about this, does the Go signal go to "0" after each transfer such that I have to toggle it back to "1"?
I tried doing that but it didn't work.
Could you provide exactly what needs to be done to send multiple... - DV 04:28 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Yes, you need to set the go bit so the dispatcher knows that the descriptor is ready to be read.
Dan -
12:17 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: HPS Memory Controller
- Hi again,
Just reading through the document. Do I have to set GO to '1' each time I update the descriptor?
Thanks!
Jack -
12:12 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: HPS Memory Controller
- Hi Dan,
I'm changing the write address in the descriptor in the VHDL. But it's still only writing to the first address and not writing to the subsequent address that I changed to. Is there something else that I have to do to update th... - Dear Sirs,
I have to use a GPIO bank over FPGA to route some interrupts (let's say 8) through the fpga to the DSP.
For the purpose, I have used the call to tcDspFpgaGpio::ConfigurePin() method and subsequently SetISRCallback() method t... - PD 12:55 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Compiling the HelloWorld application with CGT
- Thanks Mike,
I will try that out. However for the time being, I am continuing with CCS on Windows. :)
Regards
Prashant
12/09/2013
- DV 03:53 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Hi Jack,
Park Writes – When set the dispatcher will continue to reissue the same descriptor to the write
master when no other descriptors are buffered.
Yup, the address is part of the descriptor along with control signals.
For ... -
03:37 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: HPS Memory Controller
- Hi Dan,
What's parked write? Is that just writing to one address only?
Is the descriptor like an address line?
For our project, we have a signal (Data Ready) and whenever it goes to zero, there is a 16 bit data that comes in. I ... - DV 02:26 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Hi Jack,
Each packet needs its own descriptor, unless you are using parked writes. The descriptor is what tells the SGDMA component where to write that packet to, so the second packet will stall until another descriptor is pushed onto... -
02:15 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: HPS Memory Controller
- Hi,
Just a question with regarding sending these data as a package.
I know that the data in the package will be stored consecutively starting from the starting address.
But if that package is ended, and I start a second package ...
12/06/2013
- DV 03:14 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HSMC to GPIO
- Hi Jack,
The 5CSX dev board follows the Altera defined pinout for HSMC so that should work.
Dan -
03:00 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: HSMC to GPIO
- Hi,
Is HSMC on base board laid out the same pin out as this particular Terasic daughter board (this is what Altera follows in their layout)
I attached the manual for the daughterboard.
Thanks!
Jack - MF 11:49 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Accessing SPI1 bus
- I don't see a SPI /dev/ entry.
Tried this (as in the example at https://www.kernel.org/doc/Documentation/spi/spidev_test.c) - GG 11:07 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Accessing SPI1 bus
- Hi Mary,
Reading and writing over a SPI bus on Linux is pretty simple. You need to open a file descriptor for the SPI /dev/ entry and use ioctl SPI_IOC_MESSAGE commands to send spi_ioc_transfer structs to the device.
Here's a for... - How do you read/write to a device on the SPI1 bus (CS1) on the ARM side? Is there an example? Can I do low level register read/writes or is there a driver?
I am using MDK_2012-08-10
I have recompiled the kernel with a custom base... - JC 09:43 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- Once you have the network connection up you can easily move files using ssh and winscp.
- JC 09:39 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- It maybe of use to you to have the usb port act as a network device so you can send files over the network. See http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Enabling_USB_RNDIS_Support.
- I have inherited development responsibility for a custom base board using an OMAP-L138F SoM. I need to get USB working in one manner or another.
The cable designed by the board originator has a USB-A type plug on it, implying that ...