Activity
From 06/27/2014 to 07/26/2014
07/25/2014
- MW 02:42 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: PCI-e Device Driver - munmap related error
- Can you post your code? Are you getting user space faults and not kernel oops, right?
Are you unmapping with the same size as with your mmap() call?
-Mike
- Posting on behalf of a customer:
I'm having some sporadic problems with the device driver I made for our pci-e device.
It works great in general but it seems like every other run, I get a segfault when trying to
close() the device...
07/24/2014
- AD 09:05 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR)
- Hi Nigel,
I don't believe there is a way to do it directly in QSYS. You may be able to patch your generated outputs to get over that hurdle. As you would expect, Altera has the normal minimum frequency requirement programmed in so u... - ND 07:59 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR)
- Hi Adam,
Thanks for the insights.
Do you know how to persuade qsys to run the DDR at a slower speed? In normal use it will not allow anything less than 300MHz.
Thanks,
Nigel.
07/23/2014
- PS 11:06 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: fpgautil read Issue
- Hi Mike,
I found the issue. I was updating the edo_out signals only when rd was going high.
From the waveform i found rd signal going high after edo_out is driven on the interface.
It really make sense when updated register v... - MW 08:42 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: fpgautil read Issue
- Can you post (or email me) you VHDL source related to the loopback register?
Do you have Chipscope? It might be worth using chipscope to track the address / register data through the transfer cycle.
-Mike - I'm using MityDSP-L138 Board. I have implemented a Custom IP in the FPGA board.
I'm using the CS5 ARM Chipselect and using the frame work available in fpga/vhdl directory.
Also, i'm using the fpgautil program in examples dir to read... - AD 04:19 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR)
- Hi Nigel,
You are correct, the C8ES devices do not meet timing with the FPGA DDR according to Quartus. The ES silicon was not qualified to any faster speed grades than C8, though it does work according to our tests. We designed the ... - Although your reference design using FPGA DDR compiles as supplied, when I select the correct device (5CSXFC6C6U23C8ES) for my hardware I get timing violations on the FPGA DDR that I have been unable to fix.
I cannot create extra marg...
07/22/2014
- GG 11:42 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP receiving problem
- Hello Silvano,
No, the MDK uPP libraries are not setup to work with the debugger. In your code you can try setting the necessary debug bits, as you pointed out in your last post, after calling the initialize() routine. I remember hav... - SB 08:54 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP receiving problem
- The strange behaviour still continue.
When we do not send data to uPP using the FPGA the program does not have the strange stepping.
Whne we send data to uPP the stepping behaviour still remains even if the optimizations are turned off... - SB 03:10 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP receiving problem
- Thanks a lot for the suggestion.
I will check with my colleague the VHDL connection.
I also had a check at the optimitations but they are all turned off. It is very strange because it is a very simple program.
Any other suggestion, m...
07/21/2014
- Hi,
I'm using the pre-dev MitySOM eval board and I'm trying to rebuild a complete working environment with the current yocto poky distro (linux 3.12) as instructed in the wiki.
Most stuff is working but I have some open question :... - JC 12:41 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP receiving problem
- The strange stepping sounds exactly like when optimizations are turned on.
- DR 11:46 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP receiving problem
- I'm not a VHDL guy, so I can't say whether this will work as you have it. It sounds like you and your VHDL guy should sit together and verify that it is correct. It's best to do this using ChipScope.
I'm not sure why the code is ste... - SB 11:34 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP receiving problem
- Here you can find the VHDL sources.
I cannot help you a lot with VHDL becuse it is developed by a colleague of mine.
Thanks in advance another time to help me.
Silvano - SB 11:19 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP receiving problem
- Thanks a lot.
Now the working principles are clearer.
The problem now is that the software has a strange behaviour.
During the debug operations and the step by step execution, sometimes, after the receive() call, it steps itself back ... - DR 11:09 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP receiving problem
- Each time you call receive, a DMA is set up to fill the buffer you pass. Once that DMA completes, no data will be transferred into memory until another DMA is queued up.
Typically, you will queue up 2 DMA's and as each completes, ano... - SB 10:08 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP receiving problem
- Ok thank you.
I will try to change all the interrupt levels.
Another question is: but once the buffer is filled? What happens? It stops to receive?
Thanks. - DR 10:05 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP receiving problem
- I don't see any reason that it wouldn't work, but I have seen issues with some interrupt levels not working. I strongly recommend that you try some different ones.
The receive command is the start from the software point of view.
... - SB 09:59 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP receiving problem
- Thanks to have a look.
I have the signal enable and start always active.
I think that therefore is right to set bChanAUseStart to true.
I can check all the interrupt level... but i do not think that is a problem.
But supposing the co... - DR 09:49 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP receiving problem
- A couple of things that I see are different from some code that I have working here:
I use nHWInterruptLevel = 7. Perhaps level 4 is already in use...
I use nTskPriorityChanA = 11.
I don't use bChanAUseStart = true. I set this to ... - Dear all,
I am trying to use to uPP to receive data coming from the FPGA.
Attached you can find the code I wrote. Aim of the code should be:
- receive only on the channel A.
- the receiver buffer is 4096 lines and each lines is m...
07/20/2014
- Hi,
I originally wanted to connect to the board either usb storage peripherals or webcams-like peripherals. I bought a MiniUSB-B to Standard-A receptacle adapter. When I try to connect a simple USB stick, it is neither recognized nor...
07/17/2014
- DV 05:08 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Pre production (-X) modules with newer sd image
- That update to the conf/local.conf should fix the uImage issue. As for the building of the DTB through yocto, we pushed a patch to our git server about a week ago that should of addressed that issue, patch: http://support.criticallink.co...
- PB 03:42 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Pre production (-X) modules with newer sd image
- Thanks a lot for the feedback.
I have noticed that the Yocto wiki has just been updated concerning the uimage format.
For the rootfs tarball, I intended to do what you proposed but I wasn't selfconfindent. Your post helps me !
Kind ... - ND 09:13 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Pre production (-X) modules with newer sd image
- I am currently working through the kit and having a similar experience. The following seems to work for me in regard to your yocto question.
Add the files from the modules image to the core image - same directory (lib/modules/3.12.0-x...
07/15/2014
- PB 06:28 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Pre production (-X) modules with newer sd image
- Well, the orange LED switches OFF because with this new version of the SD card, the FPGA is loaded with a firmware at u-boot time. OK
I still have open questions, among them :
- I'm unable to recreate the dtb file I can find on the... - NP 04:39 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Hi Jonathan,
Thank you for your patches, it's working for me!
I have applied and successfully rebuilt my kernel.
And almost PRU example from TI can run on my board.
Thanks you very much! ^^
_Regard,
Manh BT
07/14/2014
- JC 11:39 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Ngoc,
Can you confirm that this is working for you and i'll move the changes into our main kernel branch?
I also created a wiki page to help future projects [[Using PRU]] - JC 10:51 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- gpioToggle test passed when i just ran it. Not sure why.
- JC 10:24 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Reran some of the commands to see which fail. The ./PRU_memAccessL3andDDR can cause system segfaults as it appears to use a fixed part of ddr during its test and if a program or linux happens to be residing there then it will be overrid...
- JC 09:11 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Running through all the examples, atleast one of them seems to have caused a system segfault as not even reboot was able to run afterwards.
- JC 09:09 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Hi Ngoc,
I have been working on getting this to work. So far i've integrated the patches which i've posted to a test branch until we can confirm its working. Please checkout 'mitydsp-linux-v3.2_pruss_wip' branch. Currently it is cr... - NP 04:45 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Hi,
Thank you, I'm waiting for your patches. ^^
Regards,
Manh BT - JC 09:43 AM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- Yeah by using the ti_ 335x include files I was hoping to greatly simplify our config file. Hopefully it hasn't caused more confusion then it needed to.
-
09:31 AM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: SPI clock issues with using newest u-boot
- Ok,
I knew it had to be in there somewhere, was just a bit confused
as the original mityarm335x.h had a nice section in the file for all
that.
Thanks,
John C. - JC 09:26 AM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- Pretty sure I found "#define CONFIG_SPI" in one of the ti_ config files that get included.
-
09:25 AM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: SPI clock issues with using newest u-boot
- Yes the Micron N25Q00AA does support the 48Mhz clock. The sf erase still seems longer
but I'll need to time it get get more specific. I did notice that the mityarm335x.h
file was missing "#define CONFIG_SPI" as I though it was needed ... - JC 09:25 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uBoot and USB using L138F SoM
- I have been looking into this. It seems that it was a mistake as the added resistor isn't mentioned in our Engineering change request. I noticed the added resistor recently when I was working towards getting the OTG feature working. C...
- SE 03:28 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uBoot and USB using L138F SoM
- OK, the cable that I used was a miniAB to USB A plug which was then attached to a USB A to USB A gender changer (a little crude, but it works).
Dare I ask why did you add a pull down resistor on your revision C board if the specificat...
07/13/2014
- BD 10:18 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Hello Manh BT,
The patches Mike described are in the mainline Linux kernel (http://kernel.org/). You can search for those commit hashes via Google to see the required changes.
We are in the process of applying and testing these pat... - NP 09:42 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Hi Michael,
Thanks for your information, but where can I get above patches? Is it in Critical Link MDK ?
Regard,
Manh BT
07/11/2014
- JC 05:26 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- Also make sure your Nor chip supports 48Mhz on the spi bus.
- JC 05:25 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- Did you notice any time difference with the slower speed?
-
03:30 PM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: SPI clock issues with using newest u-boot
- I took out the CONFIG_SPI_FLASH_BAR define and it now seem to pass the long erase command.
-----------------------------------
U-Boot# sf probe 0:0
SF: Detected N25Q1024 with page size 256 Bytes, erase size 4 KiB, total 128 MiB
SF:... - JC 02:23 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- It may be perfectly fine with the generic name then.
Try changing the spi clock speed and see if you get different results. I found with the nor on our SoM the erase seemed faster when run at 1Mhz but the write was much faster at 48M... -
02:19 PM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: SPI clock issues with using newest u-boot
- I added the CONFIG_SPI_FLASH_BAR define to mityarm335x.h and the warning is goes away on the "sf probe" command.
I added the #UNDEF and then "#define CONFIG_BOOTDELAY 3" to mityarm335x.h, and this now works.
The "sf erase" command seem... - JC 01:38 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- 1) I'm not sure why its detecting it differently. Maybe the newer u-boot has a more specific driver for this chip?
Also from the README -
12:44 PM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: SPI clock issues with using newest u-boot
- Hey Johnathan,
Testing out the new spi bus changes seem fine. I do have two quick questions:
1) The original code I wrote spit out the device ID as:
-------------------------
U-Boot# sf probe 0:0;
SF: Detected N25Q00AA with p... - JC 01:30 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uBoot and USB using L138F SoM
- As per the On-The-Go spec, the mini USB adapter is supposed to tie the USB_ID pin to GND to indicate it should be put into host mode.
http://en.wikipedia.org/wiki/USB_On-The-Go#OTG_mini_plugs
http://www.amazon.com/Host-Cable-fema... - SE 12:36 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uBoot and USB using L138F SoM
- Yep, loading an image seems to be OK. Next week I'll try the whole image + rootfs and make sure that works too.
Thanks! (sometimes you just need a nudge in the right direction!) - SE 12:20 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uBoot and USB using L138F SoM
- OK, now I get it. There's no resistor on my board pulling the ID pin down to 0V. I've just put a link between pins 4 & 5 on J100 and its all OK now.
I'll try putting an image on there for it to boot from and let you know. - SE 12:07 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uBoot and USB using L138F SoM
- The number is 80-000286RI-2
REV B
S/N 132556
Which bootloader are you using? I've been using my own compilation but that is wholly based on the one taken from the Git repository from your wiki link with no modifications. - JC 12:05 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uBoot and USB using L138F SoM
- Whats the part number of your dev kit? Should be a 80- number.
- JC 12:03 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uBoot and USB using L138F SoM
- I just tested this by first plugging the flash drive into the full size usb port J102. With no luck. Then plugged drive into J100 via adapter cable and it was discovered. See log below.
- SE 11:43 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uBoot and USB using L138F SoM
- I forgot to say that I know that the USB port works because, once in Linux I can mount the drive OK and read/write files etc.
USB drive is plugged into J100 via an adapter cable. - Hi there,
I'm using the L138F SoM on a REV B Industrial I/O board and I am trying to boot from a USB drive. uBoot is configured for USB but when I try:
@usb start@
All I get is:
@(Re)start USB...
USB: scanning bus for devic... - ND 09:34 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Building u-Boot and Preloader
- I believe that the files in question need to be copied from software/spl_bsp/generated into u-boot-socfpga/board/cl/mitysom-5csx, is that correct and is there anything else that needs to be copied?
Thanks,
Nigel.
- MW 08:31 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Hi,
I think we need to add the following patches (from linus tree) to the kernel to instantiate the PRUSS drivers for the L138.
2eb2478d471e45e1d0c8bb3defbf82bf7204e13d uio: uio_pruss: replace private SRAM API with genalloc
8e0d72... - Hi everyone!
I'm using MityDSP-L138F SOM + IO Industrial Board and now trying to work with PRU subsystem of OMAP-L138 processor.
I've found some instructions from:
http://processors.wiki.ti.com/index.php/PRU_Linux...
07/10/2014
- JC 05:10 PM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- The skipping bad block is not an error but more of an info. Blocks can be marked bad from factory and during use. This is just telling you one was found and skipped over.
- BJ 04:19 PM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- The clock is working now. Thank you.
But when we flash the nand, there is an error:
root@mityarm-335x:~# flash_erase /dev/mtd7 0 0
Erasing 256 Kibyte @ 400000 -- 80 % complete flash_erase: Skipping bad block at 00440000
Erasing 2... - JC 03:29 PM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- So if this is the problem I'm thinking of. It was discovered that when we changed to the 3.2 kernel we weren't setting up the RTC and by default the RTC was using its internal clock. This clock has a much higher error than the external...
- BJ 03:26 PM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- Hey Jonathan,
Thanks again, we will definitely try this solution and let you know if it works. I would like to know what you think was the problem; it is still unclear to me if the clock on the processor chip is bad, or the kernel was... - JC 03:00 PM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- I've attached the lastest uImage but yes you can build it if you would like. Instructions are here [[Linux_Kernel]]
This should be built from git commit: e53da3cda4dba6464b5b612e865c29e93144957f - BJ 02:57 PM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- NAND read: device 0 offset 0x340000, size 0x500000
Skipping bad block 0x00780000
5242880 bytes read: OK
## Booting kernel from Legacy Image at 80007fc0 ...
Image Name: Linux-3.2.0+
Image Type: ARM Linux Kernel Image (unco... - BJ 02:56 PM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- We used the pre-build kernel image that came with the board. The kernel that in the Virtual Machine/home/mitydsp/project/linux-mityarm-335x is already updated through git. I will post the boot log below. Is this fix need us to rebuild th...
- JC 08:12 AM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- What version of the kernel came with your devkit? Could you post a boot log?
Particularly I want to know if your kernel is new enough to have this fix. http://support.criticallink.com/gitweb/?p=linux-mityarm-335x.git;a=commit;h=7fae5... - ND 02:23 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Breaking changes on early MityARM
- Should have spotted that note but somehow managed to miss it!
Thanks,
Nigel. - MW 02:00 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Breaking changes on early MityARM
- Hello Nigel,
Sorry about that. The description of the hardware changes for the Dev Kit baseboard are here:
https://support.criticallink.com/redmine/projects/5csxbase/wiki/Errata_and_Product_Change_Notifications
The only signifi... - I have an early MityARM module and dev kit. On trying to implement the latest software versions I found that the Ethernet interface was not functional. On investigating it appears that there has been a pcb change on the RGMIII_RESETn sig...
- I am just revisiting the development kit after working on other projects and I am trying to locate the copy_files.sh script that is referenced on the building u-Boot wiki page.
It is not in the tools/scripts folder, or anywhere else t...
07/09/2014
- JC 05:12 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- Just pushed a fix for this.
http://support.criticallink.com/gitweb/?p=u-boot-mityarm-335x.git;a=commit;h=82762ccda7286bcc7a72b51b087b3ad6742d8a5f - BJ 04:33 PM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- Here is our clock tree (in /sys/kernel/debug/clock/summary):
clock-name parent-name rate use-count
ehrpwm2_tbclk none 0 1
ehrpwm1_tbclk... - BJ 04:14 PM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- When we boot into Linux and use the "date" (system clock) and "hwclock" (RTC I assume) commands to set/ask for time, we notice that the time changes by an hour / day (from what the actual time should be). So, for example, if we set both ...
- MW 08:02 AM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- Hi,
What do you mean by "hardware and software" clocks. Are you using the RTC or just the system clock? Can you dump your clock tree?
Are you running a heavy processor load or kernel module that may be blocking interrupts?
Nor...
07/08/2014
- Hello,
We bought a MityARM335x dev kit months ago. We have noticed that the time on the board (both software and hardware clocks) drifts by about 1 hour per day. Is this a common problem? Did we get a defective board? Are there any kn... - Hi,
I'am just starting to discover the eval kit. The one I ordered from Mouser was a pre-prod (- X) version. I understand from the errata sheet that the identified issues are not a problem for me (FPGA DDR, QSPI Nor, RVB LED).
I have...
07/07/2014
- Hi,
Do you have sample c/c++ program to read/write a memory inside Cyclone V FPGA through hps2fpga bridge interface?
Thanks.
07/03/2014
- AD 05:14 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- Hi Bill,
Sorry for the confusion. The latest image updated the Baud Rate to 115.2kbps to be consistent with the rest of the Critical Link modules.
- Adam - BL 05:05 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- Hi,
I downloaded the sd_image_mitysom_5csx_rev1B.zip, and extracted out the .bin file. Then I typed "sudo dd if=sd_image_mitysom_5csx_rev1B.bin of=/dev/sdb bs=1M" into a brand new 8GB MicroSDHC sd card. Next, I typed "sync" as instruc... - UF 02:45 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP delay between transmissions
- It was a cache invalidation issue. Calling BCACHE_wb() solved the problem.
I did find a small bug in the trasmit() code: - DR 08:29 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP delay between transmissions
- My first thought on seeing this is that it is probably a cache issue. After you set the values in the buffer, the values are in the cached version of the buffer, but haven't be written to external RAM. When you do the DMA, it doesn't g...
- SB 11:16 AM MityDSP (TI TMS320C6xxx Based Products) Software Development: RE: Problem compling with the MDK, unresolved symbols
- I got a similar problem reported here.
https://support.criticallink.com/redmine/boards/8/topics/4002
Can someone help me?
Silvano - Dear all,
I have a problem with Code Composer 6 and my DSP/BIOS project (called "quadra").
I have a first file (called "main.cpp") with the main() and a reference to a simple empty function defined in "pippuzzo.h" and called _dataIO(...
07/02/2014
- AB 09:27 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- Information on how to make an SD card based upon the current Development Kit SD card image (Rev 1B) can be found on this wiki page (https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Building_SD_Card_Image) in the "Develo...
- BL 06:17 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- Mike,
I think you meant "memtool -32 0xFFD0501C=0x06" for brgmodrst register. The reset value of the register somehow shows "0x00000000". So, I set it to 0x7, then 0x6, to make sure the hps2fpga bridge get reset and release the reset.... - MW 08:52 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- For reference on the reset register:
http://www.altera.com/literature/hb/cyclone-v/hps.html#reg_default_component/register_rstmgr_brgmodrst.html
- MW 08:51 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- Hi Bill,
It looks like you are using version 3.8 of the kernel. Version 3.8 does not have the FPGA bridge drivers that provide the sysfs layers.
I believe we are now shipping DevKits that use a 3.12 version of the kernel as the ba... - UF 06:47 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP delay between transmissions
- We cannot get the uPP to work. For test we just use the FPGA to pass the uPP pins to FPGA output pin. The Enable pin works fine, but the Data pins make no sense. Attached is an image showing the Enable pin in pink and a data pin in blue....
- MW 07:19 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP delay between transmissions
- Ah, yes, I am sorry I forgot about the EMIFA scheduling delays. You are correct.
If you are using the reference Platform.tci DSP/BIOS configuration from the BSP, try the "IRAM" section.
I believe the L2 (256K total) is setup as 1... - UF 12:55 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP delay between transmissions
- We started with EMIFA. We got a delay of 11uSec between transfers as discussed in this post:
https://support.criticallink.com/redmine/boards/12/topics/3903?r=3942#message-3942
This seems way slower than your expectations. Removing ... - SB 11:49 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Linker error on DSP application with Code Composer 6
- Thanks a lot to everybody.
It was a simple linker problem.
Silvano - Hello everybody.
We see an unexpected behaviour during simple debugging operations.
/*
* main.c
*/
#include <stdio.h>
#include <std.h>
#include <log.h>
#include "testcfg.h"
int pippi[1000];
Void main(void)
{
shor...
07/01/2014
- JC 04:30 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Linker error on DSP application with Code Composer 6
- Note i found the generic c674x device under target: generic devices
!DSP_C674x.png! - GD 03:39 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Linker error on DSP application with Code Composer 6
- Silvano,
Have you followed our guide to building a Hello World application?
https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/DSP_Hello_World
The steps for setting up a proper build environment and building D... - Dear all,
we are trying to build a simple application on DSP using Code Composer 6 plus DSP/BIOS.
In the following the very simple code:
/*
* main.c
*/
#include <std.h>
#include <log.h>
#include <stdio.h>
#include "Testcf... -
09:49 AM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: SPI clock issues with using newest u-boot
- U-Boot# sf probe 0:0
SF: Unsupported flash IDs: manuf ff, jedec ffff, ext_jedec ffff
Failed to initialize SPI flash at 0:0
U-Boot# sf probe 1:0
SF: Unsupported flash IDs: manuf ff, jedec ffff, ext_jedec ffff
Failed to initialize SPI... -
09:49 AM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: SPI clock issues with using newest u-boot
- Jonathan,
I checked with manufacturing and they do use the command in verification
of basic communication with the SPI flash. So would it be possible to get the
sf command into the main line again? My testing shows that with th...
06/30/2014
-
05:06 PM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: SPI clock issues with using newest u-boot
- Following your lead and my hardware engineers suggestion we did a temporary check and set 0x44E00050
(CM_PER_SPI1_CLKCTRL Register)to a 0x2 (it was a zero) to enable the SPI1 clock. Our system came up
and is running. I'll try and fix ... - JC 05:03 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- Committed change.
http://support.criticallink.com/gitweb/?p=u-boot-mityarm-335x.git;a=commit;h=bc7833792442421a60e74ef2dc871429b34448fe
Tested in u-boot. - JC 04:54 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- I'm testing this change right now and am going to push a commit if it works.
-
04:48 PM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: SPI clock issues with using newest u-boot
- Thanks. Let me take a look and if it works.
- JC 04:45 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- I think I found the problem. The memory address 0x481A0000 refers to McSPI1 and only spi0 is enabled in the u-boot.
In the following file in the enable_basic_clocks function:
arch/arm/cpu/armv7/am33xx/clock_am33xx.c
You should be... -
04:40 PM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: SPI clock issues with using newest u-boot
- We had originally set up to boot out of SPI NOR and on occasion do use that ability for
manufacturing testing. The biggest thing at this point is trying to resolve why we have
a SPI bus dependency on the old u-boot. - JC 04:16 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- No since booting from the spi nor on our SoMs doesn't work and I wasn't aware of anyone using the nor, I didn't look into getting it functioning in u-boot. Do you use the spi nor?
Looking at board/ti/am335x/board.c it looks like TI a... -
03:40 PM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: SPI clock issues with using newest u-boot
- Hey Jonathan,
Looking at your release without any of my mods, serial NOR was removed (no sf commands.) Was there
anything specific as to why it was removed? When I enable the SPI, I do get the sf commands back but they
are unstab... - MW 04:18 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP delay between transmissions
- Have you tried just writing to the FPGA via EMIFA? That would be a 16 2-byte word transfer. Even with 10 wait states (using 100 MHz EMIFA bus), that would be < 2 usecs. I think by default we use 5 wait states with address demuxing opt...
- UF 03:11 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP delay between transmissions
- Re-architecting our code is not really a vaiable solution. We have a feedback loop running in the DSP, that depends on data that should be read from the FPGA and be used to generate the next packet. The DSP loop is too complicated to be ...
06/28/2014
- GG 04:22 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP delay between transmissions
- Hello,
First of all, using such small packet size you may not be able to completely eliminate the delay between sending packets. There is an overhead associated with programming the uPP DMA engines. So, you may want to consider the p...
06/27/2014
- BL 09:52 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- Hi Mike,
I attached 2 files as you indicated in your previous reply. One is boot.log and another one is foo.txt.
Let me describe my intention and building flow to you.
1. I have a function need to be implemented in FPGA with HPS b... - MW 07:56 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- If you can't see the enable file then the driver for the device isn't compiled in or the device tree blob doesn't instantiate it. You typically don't want to enable the bridge until the FPGA is loaded.
Can you attach your full boot l... - We are trying to use uPP to send data from the DSP to the FPGA. The problem is that there is a delay of about 8 micro seconds between packets being send.
This is the code we use in the DSP: - JC 08:26 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- It's possible or even probable that name of the pound defines changed in this version. You can check the Readme to see if they are listed otherwise might need to grep for them.
Also take notice that at the end of the config there is ... -
04:41 PM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: SPI clock issues with using newest u-boot
- Hey Jonathan,
Do I only need the "#define CONFIG_SPI"? I've tried that along with (from the original mityarm35x.h)
the following no luck:
/* SPI support */
#ifdef CONFIG_SPI
#define BOARD_LATE_INIT
#define CONFIG_OMAP3_SPI
... - JC 04:29 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- It does look like SPI was not enabled in the new u-boot config. Checkout the differences in include/configs/mityarm35x.h between the new and old. This was done since u-boot doesn't need access to any spi devices so we left it up to lin...
-
02:36 PM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: SPI clock issues with using newest u-boot
- After moving to the newest u-boot we are having issues running SPI bus. Accessing the McSPI registers (0x481A0000) causes a data
abort. This suggests that the clocking is no longer set up correctly and that we have a dependency on u-boo...