Activity

From 11/01/2014 to 11/30/2014

MW 07:46 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Writing to HPS memory: I would recommend contacting your Arrow FAE or Altera for help with the device tree generation / sopcinfo file.
You will need to create a new preloader and uboot and device tree block. You may also need to rebuild the kernel with the... Michael Williamson
VG 07:39 AM MitySOM-5CSX Altera Cyclone V FPGA Development: Writing to HPS memory: Hi,
I'm want to use the hps_ddr_write_example design from critical link and test it on Arrow Terasic Cyclone V SOCKit .
I have changed the device and the HPS DDR3 parameters in the Quartus project.Also I'm using the Arrow kit's DDR3 ... Vidya Govindan

CC 09:23 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: inotify issue: This is a non-problem. It is working fine. Sorry for the trouble. Chris Coonan
JC 09:12 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: inotify issue: Could you provide some example code that shows the problem you are having? Also need a better explanation of what problem you are seeing.
I am not aware of anyone here who has tried using inotify on the L138, so providing us with a ... Jonathan Cormier
CC 07:31 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: inotify issue: My mistake. Cut and paste error. The kernel is 2.6.34-RC1.
Chris Coonan

CC 12:09 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: inotify issue: Trying to get inotify to execute properly from inside my application code. I am using linux kernel 2.24-RC1.
Are there any known issues with this, or do I have a configuration problem? Any help greatly appreciated.
Thanks,
Chris... Chris Coonan

GG 05:16 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: FPGA configuration via u-Boot problem: You can also use the promgen command to generate a bin file from a bit:
promgen -w -p bin -u 0 filename.bit -o filename.bin
\Greg Gregory Gluszek
02:35 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Kernel Driver: Hi
I compiled the kernel driver with the Linux kernel in the instruction here (https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Linux_Kernel).
Now I'm getting this error:
fpga_uinput: version magic '3.12.0-g456... Anonymous
MW 07:29 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: PlanAhead issue: For ISE (and I think ISE / PlanAhead are still the tools for Spartan 6, as the Vivado tools are for 7 series and higher), if you analyze your design with commercial temp and keep the non-commercial parts within their rated voltages and t... Michael Williamson
OM 03:21 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: PlanAhead issue: Hi,
Why at creation of the project in PlanAhead 14.7 for the chip xc6slx45csg324-3 it is not possible to specify Temp Grade I (only C)? In fact according to the specification on L138-FI-236-RL-ND it works in a range-40°C ~ 70°C.
Best... Oleh Mela

SK 07:51 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: FPGA configuration via u-Boot problem: Hey,
I solved the problem.
It's important that the FPGA config file <fpga>.bin file was created correctly.
By using Xilinx Impact I selected the following options in the "Create PROM file" dialog:
1. Generic Parallel PROM
2. ... Stefan Krassin
SK 07:30 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: FPGA configuration via u-Boot problem: Hi all,
I have a problem with the configuration of the FPGA and booting linux.
I followed the instructions from CL "Using u-Boot to load the FPGA".
If I run the boot command "bootcmd=sf probe 0; sf read 0xc0700000 0x100000 0x280... Stefan Krassin

04:26 PM MitySOM-5CSX Altera Cyclone V Software Development: Kernel Driver: Hi,
I'm trying to lad a kernel driver by following example on this page https://github.com/zhemao/interrupt_example
However, after run "insmod fpga\_uinput.ko" I get the following error.
fpga_uinput: version magic '3.9.0-00161-g... Anonymous

02:38 PM MitySOM-5CSX Altera Cyclone V Software Development: SOCKIT GSRD: Hi,
For my project, I'm trying to use precompiled Linux libraries with Sockit as seen in this link "http://rocketboards.org/foswiki/Documentation/ArrowSoCKITEvaluationBoardLinuxGettingStarted#Creating_an_SD_Card_using_a_Windows_Host"
... Anonymous

DG 01:52 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Real time SATA writes: Hi Mary,
As you suspected in your original post, it is likely that when you are calling fwrite, in some cases the write cache is full and is causing full flush down to storage (NAND). In this case it will take longer than just writing... Dominic Giambo
MF 01:04 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Real time SATA writes: After further testing and setting optimization, I have narrowed down the delay:
The call to fwrite() normally takes about 2.5 msec, but occasionally (on the order of minutes) this call can take 20 msec, 40 msec, 150 msec, or even 300... Mary Frantz

DV 02:22 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Modular SGDMA: Hi Jack,
We don't have any explicit examples of this but you will want to look into the userspace I/O driver. This should allow you to map in the FPGA interrrupts to a /dev/uio device.
I did a bit of searching and this looks like a... Daniel Vincelette

01:40 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Modular SGDMA: Hi Dan,
The issue seems to be with the polling. I brought out the empty signal to an oscilloscope and found that it is on, but for some reason I'm not reading that on the software side.
I think it's better to switch to interrupt to... Anonymous

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