Activity
From 03/01/2015 to 03/30/2015
03/26/2015
- JC 11:21 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Pull-up Enable for MityDSP L138 (cp[0])
- To be more specific, @CP[0]@ covers the following pins: @GP0[8] (OMAP_GP0_8), GP0[9] (OMAP_GP0_9), AHCLKX (AUDIO_SYSCLK), AHCLKR (AUDIO_SYSCLK), AFSX (AUDIO_FRAME), GP0[13] (OMAP_GP0_13), ACLKX (AUDIO_CLK), GP0[15] (OMAP_GP0_15)@
* T...
03/25/2015
- CB 10:57 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Mity L138F FPGA -> OMAP interrupt lines
- Hi Alex,
I was using MDK_2012-03-12 and in the included UCF the IO standard on those pin was different:
NET "o_nmi_n" LOC = "N8" | IOSTANDARD = LVCMOS33;
NET "o_int<0>" LOC = "K6" | IOSTANDARD = LVCMOS33;
NET "o_int<1>" LOC = "F2... - I'm trying to get a new hardware design up and running with the MityDSP L138, using the Industrial IO board as a starting point. I've noticed that in U-Boot, the enables set at DAVINCI_PUPD_ENA for groups 5, 8, 9 and 15 are set to 0 (di...
03/23/2015
- AB 05:08 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Mity L138F FPGA -> OMAP interrupt lines
- Chris,
Hopefully you happened upon this on your own but the details for the pin-configuration, voltage standards, can be found in the sample .ucf files we provide in the MDK BSP (https://support.criticallink.com/redmine/projects/arm9-...
03/12/2015
- AB 11:06 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: FPGA serial programming interface
- We are happy to provide further assistance with this issue, however I will be contacting you directly at your e-mail address that is on-file.
Thank you.
Alex
03/11/2015
- SB 10:23 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: FPGA serial programming interface
- Thanks for the information.
We are prototyping a future product and due to pin count restrictions we can't use parallel slave mode.
How are the two resistors called, Rxxx and Ryyy ? - AB 10:18 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: FPGA serial programming interface
- I discussed this with one of our engineers here and it may be possible however they is likely a bit of work required in order to make it functional.
As well he wanted to know what the reasoning is behind programming the FPGA in the Sl... - AB 08:32 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: FPGA serial programming interface
- SB,
I apologize.
The M0 and M1 FPGA pins are tied to resistors on the module to GND (M0) and 3.3V (M1) forcing the mode to Slave SelectMAP. The CCLK and DIN connections are tied to the OMAP-L138 processor.
It may be possible to...
03/10/2015
- SB 05:04 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: FPGA serial programming interface
- I understand that. However, I would like to configure the FPGA in serial slave mode.
- AB 05:01 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: FPGA serial programming interface
- SB,
The FPGA is configured using 8 bit parallel slave select mode via the EMIFA bus connection to the Omap L138 processor.
Please reference this Wiki page for information about programming the FPGA: https://support.criticallink.co... - hi,
are the pins CCLK, DIN and the MODE pins available on the OMAP-138 as GPIOs, or are they open/hardcoded on the PCB.
SB
03/06/2015
- MW 08:05 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: U-boot not bringing Linux kernel up correctly
- So this commit in u-Boot must also be accompanied by a patch in the kernel that is present in the 3.10LTS, 3.16 and higher kernels from rocket boards. This is the patch to the commit in the kernel needed for the u-Boot commit to work pr...
03/05/2015
- FC 05:20 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Write to SharedMem from DSP and read it from ARM
- Thanks for the cache info. Completely missed that part.
I reverted to the original code, and I've added BCACHE_wb() call after I write to memory on the DSP side, but I still have a problem somewhere.
I changed the SHARED_MEM_BASE t...
03/04/2015
- CW 06:44 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Very high TX packet loss on gigabit Ethernet
- Hi Mike,
I don't think those pins are associated with an IO bank. In the pin planner the default setting for those pins is the 2.5 V I/O standard, when they should be 1.8 V. Fixing this (and any other pins that were set to their defau... - MW 06:24 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Very high TX packet loss on gigabit Ethernet
- Hi Chris,
Can you expand a bit? Do you mean the IO bank voltage settings were not correct?
-Mike
- CW 05:58 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Very high TX packet loss on gigabit Ethernet
- Hi Mike,
I/O parameters turned out to be the problem. They were set to their default values (higher than they should have been). Doing the pin assignments properly seems to have fixed the problem, U-Boot is working without a hitch now...
03/02/2015
- JC 04:47 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: MAX3100 (SPI to UART bridge) driver not working
- Bindu,
You can look at how the other baseboard_spi0_slave_info have the irq filled in. Its possible that simply not setting the value might be the correct action. - BJ 04:44 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: MAX3100 (SPI to UART bridge) driver not working
- Jonathan,
Thank you for the answer; using the following helped with respect to creating the /dev/ttyMAX0: - JC 09:50 AM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: MAX3100 (SPI to UART bridge) driver not working
- The init driver gets called when the driver is added to the kernel. If its built in then this happens early on, if its built as a module then this happens when you insert the module. The probe function gets called when the driver gets ...