Mity CPU Platforms

06/17/2020

MM 09:04 AM MitySOM-5CSX Altera Cyclone V FPGA Development: mitySom 5csx and opencl 19.1

Hello,
I have a MitySom 5csx and I am trying to run the opencl helloworld program described here:
https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/MitySOM-5CSX_DevKit_OpenCL_BSP,
The version I want to use is ... Matthieu Moretti

06/04/2020

CF 06:27 PM MitySOM-5CSX Altera Cyclone V Software Development: Build Preloader failed in Windows 10

Hello,
We used to be able to build preloader in Windows 7 environment. However, not any more after we upgraded to Windows 10. Same u-boot package and same build procedures. So we think the OS change might be the course for the failur... chad fan

06/03/2020

JC 06:47 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: GPIO toggling/chattering while performing NAND read.

Worked on this with Zafer. Posting this to tie up the public post.
The solution to this is to pinmux the gpio0_27 pin in the MLO as a gpio.
Note that all the AD pins will be driven as outputs during the ROM bootloader. This can n... Jonathan Cormier

05/28/2020

JC 05:19 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: GPIO toggling/chattering while performing NAND read.

Zafer Elbi wrote:
> Have you had any chance to create the problem on your side, I mean since the discussion started?
> ...
Sorry, a few fires came up and this got forgotten. We are currently looking to see if we can get the resources ... Jonathan Cormier

05/27/2020

ZE 07:12 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: GPIO toggling/chattering while performing NAND read.

Have you had any chance to create the problem on your side, I mean since the discussion started?
ZE
From: Elbi, Zafer
Sent: Tuesday, May 26, 2020 4:04 PM
To: 'redmine@criticallink.com' <redmine@criticallink.com>
Subject: RE: [ARM ... Zafer Elbi

DR 03:33 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPGA programming problems

I will do that.
Thank you very much Dan.
Dario Dario Russo

DV 02:33 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPGA programming problems

Hi Dario,
You could also try using the "sync" linux command after you copy the rbf over. That should flush anything out to the SD card. I normally do a sync and a reboot after updating the RBF. Seeing as the filesystem is read/write d... Daniel Vincelette

DR 02:15 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPGA programming problems

Hi Dan,
Don't worry, I really appreciate your help.
Yes, running “reboot” works and it is the only way to change the FPGA configuration without rebooting the system multiple times. Indeed, even if I change the rbf and then I turn the ... Dario Russo

DV 12:53 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPGA programming problems

Hi Dario,
My apologizes for the later reply, it was a long holiday weekend in the states.
So by running "reboot" after copying over the RBF fixed your problem?
Dan Daniel Vincelette

05/26/2020

ZE 08:05 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: GPIO toggling/chattering while performing NAND read.

Yes, exactly. We did that test before.
It doesn’t show up in 2013, but shows in 2018.
Thanks
From: redmine@criticallink.com <redmine@criticallink.com>
Sent: Tuesday, May 26, 2020 3:36 PM
Subject: [ARM Cortex-A8 Based Products - So... Zafer Elbi

JC 07:36 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: GPIO toggling/chattering while performing NAND read.

Zafer Elbi wrote:
> Hello,
> ...
Hi Zafer, just to confirm that the 2013.10 u-boot doesn't chatter but the 2018 one does? Jonathan Cormier

ZE 06:47 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: GPIO toggling/chattering while performing NAND read.

Hello,
The last post was about 2 months ago. I am having exactly the same problem.
Our environment uses previous mityARM board (with single DDR2 version).
Before continuing further, I wondered if there has been any progress.
I teste... Zafer Elbi

05/25/2020

DR 08:39 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPGA programming problems

Hi Dan,
thank you very much for helping me with this problem.
Attacched you can find the boot logs for the three cases required.
The checksum verification it is ok by comparing the linux checksum with the PC file. Instead there is no ... Dario Russo

05/22/2020

DV 05:08 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPGA programming problems

Hi Dario,
Thank you for the bootlog and answering my questions.
If you are seeing the yellow led toggle in u-boot then the FPGA is reloaded from what is on the file system. There is a small chance that the file system didn't fully ... Daniel Vincelette

DR 07:59 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPGA programming problems

Hi Dan,
yes, I still have the multiple boots problem.
1) I'm not changing the SDRAM bridge configuration between builds. I'm only changing the vhdl code.
2) If I copy a new rbf file and reboot the system, the fpga will be programmed w... Dario Russo