Activity
From 06/17/2023 to 07/16/2023
07/14/2023
- JC 01:05 PM MitySOM-AM57X PCB Development: RE: Is the USB SS connection correct?
- Here is a snapshot from the devkit design in case it helps. The full schematic is available in the files section.
!clipboard-202307140903-bbh2e.png!
!clipboard-202307140904-01axr.png!
- MW 09:35 AM MitySOM-AM57X PCB Development: RE: Is the USB SS connection correct?
- Hello,
I had edited my previous post to correct. Yes it is:
Correct: AM572x (USB_TXN/P0)
The 80-001317RH-5_SCH_RevA.PDF should properly connect the USB-3. You can assume it is OK.
-Mike - MF 01:19 AM MitySOM-AM57X PCB Development: RE: Is the USB SS connection correct?
- > MitySOM-AM57 System on Module (J3, J14)) ~ HD3SS3220IRNHR (U12) ~ USB TypeC (J13) connection (SSTX_P / _N, SSRX_P / _N) is there any problem with the circuit diagram below?
> ...
Can I assume that aside from the pin names, there are n...
07/13/2023
- MF 10:39 PM MitySOM-AM57X PCB Development: RE: Is the USB SS connection correct?
- > Pin 33/35 are connected to AC11/AD11 on the *FPGA* (USB_TXN/P0), with AC coupling (DC blocking) capacitor.
Will this one also be corrected as follows?
Incorrect: FPGA (USB_TXN/P0)
Correct: AM572x (USB_TXN/P0)
- JC 02:22 PM MitySOM-AM57X PCB Development: RE: Is the USB SS connection correct?
- Correction: Replace FPGA with ARM
- MW 10:25 AM MitySOM-AM57X PCB Development: RE: Is the USB SS connection correct?
- Hi Masayoshi,
It looks like there is an error in the datasheet.
Pin 33/35 are connected to AC11/AD11 on the FPGA (USB_TXN/P0), with AC coupling (DC blocking) capacitor.
Pin 27/29 are connected to AF12/AE12 (USB_RXN/P0) as straig...
The J3Pin-Out (Table 7) of the MitySOM-AM57 System on Module data sheet describes the USB3.0 SuperSpeed terminals as follows.
Pin27 AC11 USB1_SSRX_N
Pin29 AD11 USB1_SSRX_P
Pin33 AF12 USB1_SSTX_N(2)
Pin35 AE12 USB1_SSTX_P(2)
...- SP 03:11 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Qemu pointers to try out mitysom-5csx Cyclone V Arm cortex a9 code
- Hi Dan,
Thanks for the response. We do not have an actual hardware to do basic testing of the code. We are developing an application with UBoot-uCOS - no linux.
Thank you,
Saumil
07/12/2023
- DV 06:44 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Qemu pointers to try out mitysom-5csx Cyclone V Arm cortex a9 code
- Hi Saumil,
We do not have any experience using QEMU, our development is normally done on the actual hardware.
Most of our development for the Cyclone V is done for embedded Linux. This would allow us to build for x86 and run a linu... - Hello,
Is there a wiki or any pointers to simulate using QEMU? I ran .\qemu-system-arm.exe -machine help and it lists out boards and I am not sure which one to pick.
Thank you for help,
Saumil
07/10/2023
- TC 01:57 PM MitySOM-AM57X PCB Development: RE: about MECHANICAL INTERFACE in AM57x DataSheet
- Thank you for pointing this out. We will repair the figure references in the next revision of the datasheet. In both cases the erroneous reference is to the figures directly below the text where the error appears.
https://www.criticallink.com/wp-content/uploads/60-000055-MitySOM-AM57_datasheet.pdf
On P29 and P31 of the DataSheet.
You find "Error! Reference source not found."
Please update document.
07/07/2023
- Hello,
Our application is MitySOM-5CSx based. We are trying to use FVP or QEMU for simulation during firmware development.
I have been trying to get the ARM FVP with AC5 to work but no success so far. How can I achieve this?
Thank...
06/27/2023
- MF 06:13 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Project files and Quartus startup
- Eric,
https://www.intel.com/content/www/us/en/products/details/fpga/development-tools/quartus-prime/resource.html
Here is the link to the tools. Once you select the edition/platform that is applicable to you, you can change the ver... - EN 05:43 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Project files and Quartus startup
- Thanks Mike.
That page filled in a couple of knowledge gaps for me.
I'm still struggling to find out where to get Quartus though.
Can you point me in the right direction?
I tried but was unsuccessful in getting the virtualbox... - MF 03:41 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Project files and Quartus startup
- Eric,
https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Building_fpga_181
This should be the build instructions for the project. Make sure to run the Intel Embedded Command Shell script to source the tools. This se... - MF 05:35 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Pin-muxing SPI
- Eric,
Thanks for sharing! I wasn't sure if it supported arbitrary GPIO pins or not. Good to know!
- Mike - EN 05:33 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Pin-muxing SPI
- Thanks Mike.
In case it's useful to someone else, I saw that the driver supports the use of "arbitrary GPIO pins":https://support.criticallink.com/gitweb/?p=linux-socfpga.git;a=blob;f=drivers/spi/spi-dw-mmio.c;h=447497e9124c922a4e3ecc... - MF 03:36 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Pin-muxing SPI
- Hi Eric,
Your assumptions are correct. To use the hard HPS SPI peripheral, you would use the signals you have highlighted in the attached image.
You could also not use the hard HPS SPI peripheral, and add a SPI controller into the FP... - EN 05:27 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Toolchain bundles
- Thanks Mike
- MF 03:43 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Toolchain bundles
- Eric,
Use poky-glibc-x86_64-mitysom-image-base-cortexa9hf-neon-toolchain-2.4.4.sh which is under the Quartus 18.1 20201116 section.
Sorry for the confusion. I think the other two are legacy and should be removed.
- Mike
06/26/2023
- EN 09:51 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Project files and Quartus startup
- I'm also answering my first question (how to launch Quartus).
The executable name is quartus, and it seems that I don't have a proper installation. I followed instructions on Intel's site and seem to have a broken version 20.1.
In ... - EN 04:01 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Project files and Quartus startup
- I found the answer to the second question on this page:
https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Building_fpga_181
The reference projects are in this Git repository:
https://support.criticallink.com/git... - I'm just getting started with a MitySOM-5CSX and
First off, this page says "launch quartus", and I'm not sure how.
https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/System_Design_Overview
In my ~/intelFPGA tree... - There are three poky toolchain bundles on this page, and two of them have the same name, "poky-eglibc-x86_64-mitysom-5csx-dev-kit-cortexa9hf-vfp-neon-toolchain-1.5.4.sh".
https://support.criticallink.com/redmine/projects/mityarm-5cs/f...
06/23/2023
- Hi all,
We'd like to make use of the SPI peripheral on the MitySOM-5CSx with at least two different chip-selects.
Is the use of the highlighted pins (SPIM0_SS0/SS1) the right approach?
I've worked with other SPI controller drive... - MW 08:07 PM MitySOM-AM57X PCB Development: RE: Unconnected pins, board dimensions and hole positions
- Hello.
1. Generally speaking, all of the MFIO pins are direct connects to the AM57xx CPU device and if they are unused in your design it is safe to leave them not connected. The Ball numbers are included in the table and can be cross...
Posting on behalf of customer:
1.The J1 and J3 connectors of MitySOM-AM57 are described as “MFIO” for “Type”.
"If this pin is not used, can it be left unconnected?"
(Table 6, Table 7 in MitySOM-AM57_datasheet.pdf)
2.Is it okay...