Mity CPU Platforms

06/10/2024

AK 11:40 AM MitySOM-AM57X Software Development: RE: Clock, Timer and Power Idle

Arun Krishnan wrote in message#6643:
> Solved the error by adding botton lines to to the ipc.cfg
> ...
This was not mentioned in the wiki page Arun Krishnan

AK 11:39 AM MitySOM-AM57X Software Development: RE: Clock, Timer and Power Idle

Solved the error by adding botton lines to to the ipc.cfg
var Resource = xdc.useModule('ti.ipc.remoteproc.Resource');
Resource.customTable = true;
Arun Krishnan

AK 10:51 AM MitySOM-AM57X Software Development: RE: Clock, Timer and Power Idle

When I try to build the application, I am getting the error "error #10056: symbol "ti_ipc_remoteproc_ResourceTable" redefined: first defined in "./rsc_table_vayu_dsp.obj"; redefined in "/home/xxx/workspace_v10/rtos_template_app_am572x_c6... Arun Krishnan

MW 11:08 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem

There is a cross-bar that sits between EMIFA on the L138 and the DSP / ARM / peripheral masters.
When a read request is generated by the DSP to the EMIFA space, a command/request is generated to the cross-bar controller. The controll... Michael Williamson

KB 07:52 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem

Thank you for answer.
We will conduct the above experiment later.
Currently, we are trying to increase the RD Clk speed of FIFO.
MDK_2014-01-13/sw/ARM/u-boot-mitydspl138/board/davinci/mityomapl138/mityomapl138.c
In the file abo... Kyungguk Bok

06/07/2024

PS 08:55 AM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A module SODIMM pinout documentation error

William,
I see that you have released an update to the datasheet. Unfortunately it is contradicting now. The 3rd column is changed in the respective table, but the pinmux alternatives and the BGA ball numbers are unchanged (columns 5-... Pal Szabo

06/05/2024

GG 09:05 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem

Hello,
Based on the FPGA code you shared I believe that the primary issue you are having is that your FPGA code requires transitions on i_ema_cs5_n or i_ema_oe_n in order to read out new FIFO samples. These transitions are most likel... Gregory Gluszek

KB 12:42 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem

Thank you for answer.
As you suggested, read Cache_and_Memory and
We proceeded by modifying the source as shown below. Kyungguk Bok

06/04/2024

SW 05:17 PM MitySOM-AM57X Software Development: RE: Clock, Timer and Power Idle

Thanks for the all the info John. I posted to e2e also hoping TI could provide some more info on how dmtimer and clock modules work. Probably a tutorial somewhere on there. Seems like plenty of reference material but light on user manua... Stanley Wood

JP 02:04 PM MitySOM-AM57X Software Development: RE: Clock, Timer and Power Idle

For the benefit of others, Stanley has also posted this question to an E2E forum at https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1369167/am5728-clock-timer-and-power-idle-questions.
> 1. Why the DRA7XX an... John Pruitt

06/03/2024

JC 03:08 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem

The fpga guys can step in if I've missed something but it looks to me like your missing cache invalidate calls. If the DMA engine is modifying RAM outside of the DSPs knowledge, then the DSP needs to be informed that its cache of that m... Jonathan Cormier

KB 08:57 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: FPGA (FIFO) -> DSP (DMA) transfer problem

hello.
I am posting because I have a question related to DMA.
The last CCS issue was not resolved, so I am loading the DSP application through ARM. (Thank you to those who helped.)
The work I am currently doing is accumulating data ... Kyungguk Bok

SW 03:06 PM MitySOM-AM57X Software Development: Clock, Timer and Power Idle

Reference: https://support.criticallink.com/git/mitysom-am57x-ref.git
I've built and successfully run the ex02_messageq example from the repo listed above. However I have several questions.
The ex02_messageq example seems to be the ... Stanley Wood

05/23/2024

JC 02:12 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Error Building File System

Great, glad you figured it out Jonathan Cormier

NW 02:07 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Error Building File System

Thanks Jon! NetworkManager service had actually crashed. :( Nathan Wright

JC 01:51 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Error Building File System

Hi Nathan, This line mentions it cannot reach our website: Jonathan Cormier

NW 01:31 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: Error Building File System

Hello,
I am attempting to build the file system and running in to an error.
I am here... Nathan Wright