Mity CPU Platforms

06/10/2024

11:40 AM MitySOM-AM57X Software Development: RE: Clock, Timer and Power Idle

Arun Krishnan wrote in message#6643:
> Solved the error by adding botton lines to to the ipc.cfg
> var Resource = ... Arun Krishnan

11:39 AM MitySOM-AM57X Software Development: RE: Clock, Timer and Power Idle

Solved the error by adding botton lines to to the ipc.cfg
var Resource = xdc.useModule('ti.ipc.remoteproc.Resource'... Arun Krishnan

10:51 AM MitySOM-AM57X Software Development: RE: Clock, Timer and Power Idle

When I try to build the application, I am getting the error "error #10056: symbol "ti_ipc_remoteproc_ResourceTable" r... Arun Krishnan

11:08 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem

There is a cross-bar that sits between EMIFA on the L138 and the DSP / ARM / peripheral masters.
When a read reque... Michael Williamson

07:52 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem

Thank you for answer.
We will conduct the above experiment later.
Currently, we are trying to increase the RD Clk... Kyungguk Bok

06/07/2024

08:55 AM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A module SODIMM pinout documentation error

William,
I see that you have released an update to the datasheet. Unfortunately it is contradicting now. The 3rd c... Pal Szabo

06/05/2024

09:05 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem

Hello,
Based on the FPGA code you shared I believe that the primary issue you are having is that your FPGA code r... Gregory Gluszek

12:42 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem

Thank you for answer.
As you suggested, read Cache_and_Memory and
We proceeded by modifying the source as shown bel... Kyungguk Bok

06/04/2024

05:17 PM MitySOM-AM57X Software Development: RE: Clock, Timer and Power Idle

Thanks for the all the info John. I posted to e2e also hoping TI could provide some more info on how dmtimer and clo... Stanley Wood

02:04 PM MitySOM-AM57X Software Development: RE: Clock, Timer and Power Idle

For the benefit of others, Stanley has also posted this question to an E2E forum at https://e2e.ti.com/support/proces... John Pruitt

06/03/2024

03:08 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem

The fpga guys can step in if I've missed something but it looks to me like your missing cache invalidate calls. If t... Jonathan Cormier

08:57 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: FPGA (FIFO) -> DSP (DMA) transfer problem

hello.
I am posting because I have a question related to DMA.
The last CCS issue was not resolved, so I am loading ... Kyungguk Bok

03:06 PM MitySOM-AM57X Software Development: Clock, Timer and Power Idle

Reference: https://support.criticallink.com/git/mitysom-am57x-ref.git
I've built and successfully run the ex02_me... Stanley Wood

05/23/2024

02:12 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Error Building File System

Great, glad you figured it out Jonathan Cormier

02:07 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Error Building File System

Thanks Jon! NetworkManager service had actually crashed. :( ... Nathan Wright

01:51 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Error Building File System

Hi Nathan, This line mentions it cannot reach our website:... Jonathan Cormier

01:31 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: Error Building File System

Hello,
I am attempting to build the file system and running in to an error.
I am here...... Nathan Wright