Mity CPU Platforms

07/29/2024

JC 05:36 PM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: X1 component SiLabs 590 BA100M000G depopped

See "PCN20220621000":https://support.criticallink.com/redmine/attachments/download/31707/PCN20220621000.pdf linked from https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Module_Product_Change_Notifications
This osc... Jonathan Cormier

RS 02:09 PM MityDSP-L138 (ARM9 Based Platforms) PCB Development: X1 component SiLabs 590 BA100M000G depopped

Hello,
we are working on transferring our design from the Spartan 6 build to the A7 SOM and an engineer noticed noticed that the X1 oscillator is depopped on our A7 builds. Can you confirm what this oscillator does, and if it is for ... Rachel Shaska

07/25/2024

GG 07:47 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: how to access gpio using pio ip core in c code

Hello,
I would look at the avalon memory mapped slave address in your signal tap. It's possible the hps is requesting a read from a different address for one of those two cycles. It's also possible two reads are queued up back to bac... Gregory Gluszek

07/24/2024

FW 02:31 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Serial port 2 issue, RS485, RTS drops to early

I figure it's about 10% of the CPU when operating 1200 baud and 1 response per second; it gets much lower as you approach 9600 baud (1.3%). This also takes into account the modulo 16 fifo calc assuming random packet lengths. All in all, ... Fred Weiser

BK 07:11 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: how to access gpio using pio ip core in c code

Hi,
Yes, I am verified in Signal Tap only. and as off now like, we are able to do read and write HPS to FPGA using LW_AVALON_MM interface. In case of read from HPS, avalon_slave_read signal is being high for two clock cycles. Where as... Bhardwaj Kotha

07/23/2024

GG 04:12 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: how to access gpio using pio ip core in c code

It looks like you posted a couple different versions of your C code. Which one are you running and what does the output look like? How are you verifying the FPGA is receiving data from the HPS? Are you using signal tap?
Thanks,
Greg Gregory Gluszek

07/22/2024

JC 07:21 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Serial port 2 issue, RS485, RTS drops to early

> before shutting off the 485 driver
Any idea how often the shutting down occurs? Jonathan Cormier

FW 07:19 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Serial port 2 issue, RS485, RTS drops to early

I patched the 8250.c file to increase the 10ms timeout. I found the timeout is really there only to assure the uart tx fifo drains completely before shutting off the 485 driver - as such, it will never be more than about 16 characters. I... Fred Weiser

BK 03:16 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: how to access gpio using pio ip core in c code

Hi,
In my implementation, the Avalon Memory Mapped interface automatically assigned a base address in platform designer with that address only I successfully sent an 32bit incremental data from the HPS to the FPGA and received it corr... Bhardwaj Kotha

07/19/2024

DL 06:14 PM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: MityDSP-L138F Block Diagram Inconsistencies

Dan,
That clears things up perfectly. Thank you for a quick and comprehensive response. Dylan Louviaux

DV 06:10 PM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: MityDSP-L138F Block Diagram Inconsistencies

Hi Dylan,
The external input to the Boot Config Block is the EXT_BOOT# signal pin bin 12 of the SO-DIMM connector. The Boot Config Block on the SOM uses the value of EXT_BOOT# to set the boot strap resistors for the L138. The two opti... Daniel Vincelette

DL 04:06 PM MityDSP-L138 (ARM9 Based Platforms) PCB Development: MityDSP-L138F Block Diagram Inconsistencies

All,
I am designing a carrier board for the MityDSP-L138F with A7 FPGA. I have noticed some inconsistencies with the block diagrams in the documentation (https://www.criticallink.com/wp-content/uploads/2014/01/MityDSP-L138F_Spec.pdf).
... Dylan Louviaux

DV 02:11 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

Hello,
For the reference project the makefile removes those lines from the sdc file before it does the build, if you aren't using the Makefile for doing the build then you need to manually delete those lines after running Platform Des... Daniel Vincelette

BK 06:45 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

Hi,
Yeah, I am removed that two lines in dev_5cs/synthesis/submodules/dev_5cs_hps_0_fpga_interfaces.sdc, before updating this one i am getting 30-40% of packet loss in ping , as off now I am updated that one now i am getting 5-7% of ... Bhardwaj Kotha

07/16/2024

DV 07:40 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

Hello,
I have verified that the reference design does meet timing when built via the makefile (ie make rbf). The makefile removes 2 incorrectly autogenerated clock assignments for the MAC clocks. The following lines need to be deleted... Daniel Vincelette

07/15/2024

GG 06:58 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: how to access gpio using pio ip core in c code

The most straightforward way to do that would be to create your own Platform Designer Component with an Avalon Memory Mapped Slave interface. (See https://www.intel.com/content/www/us/en/docs/programmable/683364/18-1/creating-components.... Gregory Gluszek

07/13/2024

BK 03:16 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

Hi,
with the provided reference project there is no packet loss but there are timing errors (screenshots attached) even after modified the reference project, as we said in first query, we observed similar timing errors with the same h... Bhardwaj Kotha

07/11/2024

DV 01:39 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

It sounds like you are on edge for timing so please verify that your design meets timing via TimeQuest in Quartus. Also when you used the provided reference project you did not see this packet lose, correct?
Dan Daniel Vincelette

BK 12:05 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

i had made HPS and emac Splitter Conduit signals to external in Platform Designer and I had assigned that conduit signals properly in top Module accordingly like, hps_0_emac0_phy_txd_o to rgmiib_emac_phy_txd_o and for that reference, ple... Bhardwaj Kotha

07/10/2024

DV 01:08 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

Hello,
For the case that you are seeing 60% packet lose, what did you change in the reference FPGA project that was supplied in the bnet_mps project? Also have you verified that your project is meeting timing?
Best regards,
Dan
Daniel Vincelette

BK 12:07 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: how to access gpio using pio ip core in c code

Yes, I wanted to send the 256 BITS of raw data from HPS to FPGA. Can you give me the supplies for that. Bhardwaj Kotha

07/09/2024

DV 05:44 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A module SODIMM pinout documentation error

My mistake. I completely missed the A when I saw this thread. :)
Thanks,
David David Van Sickle

MW 02:43 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A module SODIMM pinout documentation error

Hi David,
The symbol for the MitySOM-AM62 DevKit is for the MitySOM-AM62x and we have verified it is correct. The information in the thread above is for the datasheet for the MitySOM-AM62Ax.
While the DevKit board is compatible wi... Michael Williamson

DV 02:12 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A module SODIMM pinout documentation error

Hello,
This was brought to my attention and I decided to do a quick check of these pins on the AM62 Dev board schematic, which our current work is based around.
On the schematic symbol for the MitySOM_AM62: pins 99, 101, 103 agree ... David Van Sickle

07/08/2024

TI 03:09 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Get URL from jenkins file

I just did a clean pull of the kernel and built it using the poky 3.0.4 sdk with no issues.
It sounds like either there was some old/other config in the build tree or your environment is different
my build did _not_ attempt to build th... Tim Iskander

GG 01:20 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: How to access gpio using c code in yocto linux, which is created using PIO IP with HPS

This seems to be a duplicate of https://support.criticallink.com/redmine/boards/45/topics/6705. Please refer to the other linked topic for further details.
Thanks,
Greg Gregory Gluszek

GG 01:18 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: how to access gpio using pio ip core in c code

Hello,
Can you share capture of your console so we can evaluate what commands you are using and exactly what errors are being reported?
As long as you do not exceed resources on the FPGA you should be able to add the required pio ... Gregory Gluszek

07/07/2024

BK 01:01 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Get URL from jenkins file

Hi,
I have downloaded the kernel from https://git.criticallink.com/gitweb/?p=linux-socfpga.git;a=shortlog;h=refs/heads/socfpga-5.4.23-lts (branch socfpga-5.4.23-lts) and updated the device tree and defconfig files by taking them fr... Bhardwaj Kotha

07/05/2024

BK 08:53 AM MitySOM-5CSX Altera Cyclone V Software Development: How to access gpio using c code in yocto linux, which is created using PIO IP with HPS

Hi,
I have added pio ip (output only) to the HPS block design in platform designer, and modified/added gpio block with address specification by converting the dtb file to dts. Again compiled back to new dtb and replaced in pre built os ... Bhardwaj Kotha

BK 08:51 AM MitySOM-5CSX Altera Cyclone V Software Development: how to access gpio using pio ip core in c code

Hi,
I have added pio ip (output only) to the HPS block design in platform designer, and modified/added gpio block with address specification by converting the dtb file to dts. Again compiled back to new dtb and replaced in pre built ... Bhardwaj Kotha

07/04/2024

BK 07:34 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Error in u-boot. cyclone v 5CSEBA4U2317 SOM

Hi Daniel,
Now am able to generate the boot files.
Thanks & Regards,
Bhardwaj Bhardwaj Kotha

BK 07:02 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

Hi,
I donot have much resources, as my application need more resources, I wanted to use HPS EMAC. And I am not going to implement any other IP layers, I just modify the data part and forward on the other port. For this, I have made emac... Bhardwaj Kotha

07/03/2024

JC 02:19 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: MityDSP-L138 Power Draw in Deep Sleep? Waking ARM core from DSP core? Power and Sleep Controller (PSC)

Michael Bisbano wrote in message#6697:
> Hi Jonathan,
> ...
We have some posted power usage measurements for the module here: https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/33V_Supply_Requirements
A max of 1W l... Jonathan Cormier

NW 01:09 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: oe-layertool-setup.sh script seems to pull and merge when it shouldn't need to

Ok, I did. Nathan Wright

07/02/2024

JC 08:46 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: oe-layertool-setup.sh script seems to pull and merge when it shouldn't need to

I think both of these make a lot of sense. I'd recommend reporting this to TI via the meta-arago mailing list. They should even include your name as the patch author.
Here is the last patch submitted related to the oe-layertool-setu... Jonathan Cormier

NW 07:16 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: oe-layertool-setup.sh script seems to pull and merge when it shouldn't need to

while we're at it, why let it complain about detached heads when the config file asked for detached heads? Nathan Wright

NW 06:51 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: oe-layertool-setup.sh script seems to pull and merge when it shouldn't need to

We noticed in our pipeline setup that the oe-layertool-setup.sh script still appeared to be pulling and merging against a cached repo that had no changes. We are on ubuntu 24.
We think this fixes it...
diff --git a/oe-layertool-se... Nathan Wright

07/01/2024

MB 09:16 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: MityDSP-L138 Power Draw in Deep Sleep? Waking ARM core from DSP core? Power and Sleep Controller (PSC)

Hi Jonathan,
Thank you for the response, please let me know what you find out! The system as a whole must be under 1W average while operating, and very low <50mW when in sleep. When operating, it will be performing some audio signal pr... Michael B

JC 07:05 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: MityDSP-L138 Power Draw in Deep Sleep? Waking ARM core from DSP core? Power and Sleep Controller (PSC)

Michael Bisbano wrote:
> Hi all,
> ...
Hi Michael, I did a bunch of work for the MitySOM-335x for sleep mode but am not sure about the L138. I'll ask around and let you know what I find out.
>
> ...
In the meantime could you clarif... Jonathan Cormier

MB 06:34 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: MityDSP-L138 Power Draw in Deep Sleep? Waking ARM core from DSP core? Power and Sleep Controller (PSC)

Hi all,
I was wondering if anyone had data on power draw for the MityDSP-L138 in deep sleep? My application is battery powered and we are determining if it is more feasible to have an external circuit on our custom baseboard control p... Michael B

DV 06:18 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Error in u-boot. cyclone v 5CSEBA4U2317 SOM

Hello,
You shouldn't need to update the compiler or path from the default that are filled out by the bsp-editor. Did you also run into errors when you used the default cross compiler that was choosen by the bsp-editor?
Best regards... Daniel Vincelette

JC 03:49 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Serial port 2 issue, RS485, RTS drops to early

Fred Weiser wrote in message#6688:
> Changing the timer is probably not in my best interest; my project supports down to 1200 baud with packets up to 256 in length (that's over 2 seconds). I see two possibilities:
Can you try it just t... Jonathan Cormier

06/30/2024

TI 05:51 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Get URL from jenkins file

Here is a link to the SDK for the 5CSx
you will need to run it on a linux machine (ubuntu 18 and up recommended)
https://support.criticallink.com/files/socfpga/poky-glibc-i686-epstech-image-bnet-mps-cortexa9hf-neon-mitysom-c5-toolchain... Tim Iskander