Activity
From 07/11/2024 to 08/09/2024
08/09/2024
(Posted on behalf of a customer)
On my existing system, the Max10 FPGA has the USB Blaster interface that uses 2.5V JTAG levels that I also route to a CPLD on my board. From the MitySOM-C10G documentation, the 10G uses 1.8V JTAG L...
08/01/2024
- BK 12:52 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access
- Hi,
Actually that timing issues were resolved and ping performance also well as of now without packet loss. And now I am working fine with RGMII splitter connected to the HPS EMAC of latency 2 microseconds in my setup, I want to under...
07/31/2024
- TI 03:39 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Receive and send data using vlan tag
- Bhardwaj
There should be no devicetree changes necessary to use the VLAN feature of the Ethernet.
You verified that the 8021q module is loaded.
You should be able to create a VLAN interface and configure it from the shell and then add... - Hi,
I am working on ethernet using vlan. I had used the ip command to create the vlan after that some data sent from another PC having vlan and run receive code on board to receive data but we didn't get any data. when we try these e...
07/29/2024
- JC 05:36 PM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: X1 component SiLabs 590 BA100M000G depopped
- See "PCN20220621000":https://support.criticallink.com/redmine/attachments/download/31707/PCN20220621000.pdf linked from https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Module_Product_Change_Notifications
This osc... - Hello,
we are working on transferring our design from the Spartan 6 build to the A7 SOM and an engineer noticed noticed that the X1 oscillator is depopped on our A7 builds. Can you confirm what this oscillator does, and if it is for ...
07/25/2024
- GG 07:47 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: how to access gpio using pio ip core in c code
- Hello,
I would look at the avalon memory mapped slave address in your signal tap. It's possible the hps is requesting a read from a different address for one of those two cycles. It's also possible two reads are queued up back to bac...
07/24/2024
- FW 02:31 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Serial port 2 issue, RS485, RTS drops to early
- I figure it's about 10% of the CPU when operating 1200 baud and 1 response per second; it gets much lower as you approach 9600 baud (1.3%). This also takes into account the modulo 16 fifo calc assuming random packet lengths. All in all, ...
- BK 07:11 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: how to access gpio using pio ip core in c code
- Hi,
Yes, I am verified in Signal Tap only. and as off now like, we are able to do read and write HPS to FPGA using LW_AVALON_MM interface. In case of read from HPS, avalon_slave_read signal is being high for two clock cycles. Where as...
07/23/2024
- GG 04:12 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: how to access gpio using pio ip core in c code
- It looks like you posted a couple different versions of your C code. Which one are you running and what does the output look like? How are you verifying the FPGA is receiving data from the HPS? Are you using signal tap?
Thanks,
Greg
07/22/2024
- JC 07:21 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Serial port 2 issue, RS485, RTS drops to early
- > before shutting off the 485 driver
Any idea how often the shutting down occurs? - FW 07:19 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Serial port 2 issue, RS485, RTS drops to early
- I patched the 8250.c file to increase the 10ms timeout. I found the timeout is really there only to assure the uart tx fifo drains completely before shutting off the 485 driver - as such, it will never be more than about 16 characters. I...
- BK 03:16 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: how to access gpio using pio ip core in c code
- Hi,
In my implementation, the Avalon Memory Mapped interface automatically assigned a base address in platform designer with that address only I successfully sent an 32bit incremental data from the HPS to the FPGA and received it corr...
07/19/2024
- DL 06:14 PM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: MityDSP-L138F Block Diagram Inconsistencies
- Dan,
That clears things up perfectly. Thank you for a quick and comprehensive response. - DV 06:10 PM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: MityDSP-L138F Block Diagram Inconsistencies
- Hi Dylan,
The external input to the Boot Config Block is the EXT_BOOT# signal pin bin 12 of the SO-DIMM connector. The Boot Config Block on the SOM uses the value of EXT_BOOT# to set the boot strap resistors for the L138. The two opti... - All,
I am designing a carrier board for the MityDSP-L138F with A7 FPGA. I have noticed some inconsistencies with the block diagrams in the documentation (https://www.criticallink.com/wp-content/uploads/2014/01/MityDSP-L138F_Spec.pdf).
... - DV 02:11 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access
- Hello,
For the reference project the makefile removes those lines from the sdc file before it does the build, if you aren't using the Makefile for doing the build then you need to manually delete those lines after running Platform Des... - BK 06:45 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access
- Hi,
Yeah, I am removed that two lines in dev_5cs/synthesis/submodules/dev_5cs_hps_0_fpga_interfaces.sdc, before updating this one i am getting 30-40% of packet loss in ping , as off now I am updated that one now i am getting 5-7% of ...
07/16/2024
- DV 07:40 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access
- Hello,
I have verified that the reference design does meet timing when built via the makefile (ie make rbf). The makefile removes 2 incorrectly autogenerated clock assignments for the MAC clocks. The following lines need to be deleted...
07/15/2024
- GG 06:58 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: how to access gpio using pio ip core in c code
- The most straightforward way to do that would be to create your own Platform Designer Component with an Avalon Memory Mapped Slave interface. (See https://www.intel.com/content/www/us/en/docs/programmable/683364/18-1/creating-components....
07/13/2024
- BK 03:16 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access
- Hi,
with the provided reference project there is no packet loss but there are timing errors (screenshots attached) even after modified the reference project, as we said in first query, we observed similar timing errors with the same h...
07/11/2024
- DV 01:39 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access
- It sounds like you are on edge for timing so please verify that your design meets timing via TimeQuest in Quartus. Also when you used the provided reference project you did not see this packet lose, correct?
Dan - BK 12:05 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access
- i had made HPS and emac Splitter Conduit signals to external in Platform Designer and I had assigned that conduit signals properly in top Module accordingly like, hps_0_emac0_phy_txd_o to rgmiib_emac_phy_txd_o and for that reference, ple...