Mity CPU Platforms

07/21/2025

NZ 04:44 PM MitySOM-C10GX Firmware: RE: Clock on MitySOM-C10G

On the MitySOM C10G, there is an onboard 100 MHz oscillator connected to FPGA Ball Y15, which has optional function CLKUSR. This can be used for your FPGA designs clock input, as is done in our reference design with the CLK_100 signal. N... Noah Zins

TC 12:23 PM MitySOM-C10GX Firmware: Clock on MitySOM-C10G

I am new to FPGA in general so forgive me if this question is simple.
* Which pin/pins are configured in the hardware to be used as an input reference clock? Conceptually, how can I bring a clock signal to these pins if there is not a... Thomas Catalino

07/08/2025

DV 01:53 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Clarification regarding LED 4 on MitySOM-5CSX DevKit

Hello,
When you refer to the "binary," are you referring to the RBF file used to program the FPGA? If so, are you observing that the FPGA does not program correctly on the "bad" development kit—specifically, that the orange LED remain... Daniel Vincelette

AF 01:16 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Clarification regarding LED 4 on MitySOM-5CSX DevKit

Thank you for your response. I’ve updated the clock pin configuration as suggested.
However, I’m currently facing an issue:
I have two MitySOM-5CSX evaluation boards. The binary I want to test is stored on the SD card. It works perfe... Anonymous fpga

07/03/2025

SG 06:31 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Unable to program FPGA – “MSEL switch is in the wrong position” on MitySOM-5CSX dev kit

Hello,
We were able to recreate your issue with the app you were using (https://github.com/robseb/rstoolsCY5). After compiling the app and running it on the board as you did, we were able to move past your issue by setting the MSEL sw... Seth Graber

07/02/2025

AF 03:13 PM MitySOM-5CSX Altera Cyclone V FPGA Development: Unable to program FPGA – “MSEL switch is in the wrong position” on MitySOM-5CSX dev kit

I’m bringing up our new MitySOM-5CSX evaluation board and ran into an issue while trying to load the reference bitstream that ships with the kit.
1- I copied dev_5cs.rbf to the board via SCP.
2- From the Linux prompt on the board I... Anonymous fpga

MW 03:07 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Clarification regarding LED 4 on MitySOM-5CSX DevKit

I believe the spreadsheets are correct.
T13 is not connected to a dedicated clock input pin, needed to feed a REFCLK/CLK clock network. It is on pin 155 of the *SOM* connector.
HSMC2_CLK_P driving pin 155 of the *Partial HSMC* con... Michael Williamson

JM 02:42 PM MitySOM-5CSX Altera Cyclone V FPGA Development: Clarification regarding LED 4 on MitySOM-5CSX DevKit

I am posting this on behalf of a customer.
I would like to verify that th... Judy Mastracco

06/30/2025

MW 10:02 AM MitySOM-AM57X FPGA Development: RE: Requesting the source/origin for the fpga bin in the default image in the sd card provided along with the evk.

Hello,
It is the same one as documented on the [[FPGA_Example_Projects]] page. The only difference is that the target device was changed to the 50 KLE part number instead of the 15 KLE part number in the project settings.
Please l... Michael Williamson

TR 05:32 AM MitySOM-AM57X FPGA Development: Requesting the source/origin for the fpga bin in the default image in the sd card provided along with the evk.

Hi,
We are working currently with the AM57 devkit with FPGA and using the sd card image provided along with the evk.
Our query is regarding the *fpga_7a50t.bin* file in the image.
Specifically, if there is any source project avai... Thejas Raj