Mity CPU Platforms

07/21/2025

NZ 04:44 PM MitySOM-C10GX Firmware: RE: Clock on MitySOM-C10G

On the MitySOM C10G, there is an onboard 100 MHz oscillator connected to FPGA Ball Y15, which has optional function CLKUSR. This can be used for your FPGA designs clock input, as is done in our reference design with the CLK_100 signal. N... Noah Zins

TC 12:23 PM MitySOM-C10GX Firmware: Clock on MitySOM-C10G

I am new to FPGA in general so forgive me if this question is simple.
* Which pin/pins are configured in the hardware to be used as an input reference clock? Conceptually, how can I bring a clock signal to these pins if there is not a... Thomas Catalino

07/08/2025

DV 01:53 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Clarification regarding LED 4 on MitySOM-5CSX DevKit

Hello,
When you refer to the "binary," are you referring to the RBF file used to program the FPGA? If so, are you observing that the FPGA does not program correctly on the "bad" development kit—specifically, that the orange LED remain... Daniel Vincelette

AF 01:16 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Clarification regarding LED 4 on MitySOM-5CSX DevKit

Thank you for your response. I’ve updated the clock pin configuration as suggested.
However, I’m currently facing an issue:
I have two MitySOM-5CSX evaluation boards. The binary I want to test is stored on the SD card. It works perfe... Anonymous fpga