Initial Bringup¶
- Table of contents
- Initial Bringup
Build firmware¶
Instructions based on Intel's: https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderForAgilex5
All these commands expect you to work out of the same top level directory. For example: ~/projects/agelix-5/firmware
export TOP_FOLDER=`pwd`
Install dependencies¶
Intel ran this on Ubuntu 20.02
sudo apt install gawk wget git diffstat unzip texinfo gcc build-essential chrpath \ socat cpio python3 python3-pip python3-pexpect xz-utils debianutils iputils-ping \ python3-git python3-jinja2 libegl1-mesa libsdl1.2-dev pylint3 xterm python3-subunit \ mesa-common-dev zstd liblz4-tool
Fetching the ARM Tool chain¶
cd $TOP_FOLDER wget https://developer.arm.com/-/media/Files/downloads/gnu/11.2-2022.02/binrel/gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz tar xf gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
Set your env to use the toolchain¶
export PATH=`pwd`/gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu/bin:$PATH export ARCH=arm64 export CROSS_COMPILE=aarch64-none-linux-gnu-
Building the ARM Trusted Firmware¶
NOTE: Please apply the following patch to switch the console to UART1: https://support.criticallink.com/redmine/attachments/34881
cd $TOP_FOLDER rm -rf arm-trusted-firmware git clone -b socfpga_agilex5-ES_RC https://github.com/altera-opensource/arm-trusted-firmware arm-trusted-firmware cd arm-trusted-firmware git apply commit-dadfc1a make -j 48 PLAT=agilex5 bl31 cd ..
Output: $TOP_FOLDER/arm-trusted-firmware/build/agilex5/release/bl31.bin (to used for u-boot.itb generation)
Building U-Boot¶
cd $TOP_FOLDER rm -rf u-boot-socfpga git clone -b socfpga_agilex5-ES_RC https://git.criticallink.com/git/u-boot-socfpga.git cd u-boot-socfpga make mrproper make socfpga_agilex5_defconfig # link to ATF ln -s ../arm-trusted-firmware/build/agilex5/release/bl31.bin make -j 48 aarch64-none-linux-gnu-objcopy -I binary -O ihex --change-addresses 0x0 spl/u-boot-spl-dtb.bin spl/u-boot-spl.ihex
Building FPGA Project¶
Build the FPGA project as usual, qsys top level is called mitysbc_a5e.qsys. Build with Quartus 23.4.
Build the HPS SOF¶
Required:- U-Boot is already built
- FPGA project is already built
- Copy the $TOP_FOLDER/u-boot-socfpga/spl/u-boot-spl.ihex into your top level FPGA project
quartus_pfg -c output_files/mitysbc_a5e.sof mitysbc_a5e_hps.sof -o hps_path=u-boot-spl.ihex
Output: mitysbc_a5e_hps.sof
Building The kernel¶
cd $TOP_FOLDER rm -rf linux-socfpga git clone -b socfpga_agilex5-ES_RC https://git.criticallink.com/git/linux-socfpga.git linux-socfpga cd linux-socfpga make defconfig make -j 48 Image && make intel/socfpga_agilex5_socdk.dtb
Building Yocto¶
cd $TOP_FOLDER rm -rf yocto && mkdir yocto && cd yocto git clone -b nanbield https://git.yoctoproject.org/poky git clone -b socfpga_agilex5-ES_RC https://git.yoctoproject.org/meta-intel-fpga git clone -b nanbield https://github.com/openembedded/meta-openembedded source poky/oe-init-build-env ./build echo 'BBLAYERS += " ${TOPDIR}/../meta-intel-fpga "' >> conf/bblayers.conf echo 'BBLAYERS += " ${TOPDIR}/../meta-openembedded/meta-oe "' >> conf/bblayers.conf echo 'BBLAYERS += " ${TOPDIR}/../meta-openembedded/meta-networking "' >> conf/bblayers.conf echo 'MACHINE = "agilex5"' >> conf/local.conf echo 'KERNEL_PROVIDER="linux-socfpga-lts"' >> conf/local.conf echo 'EXTRA_IMAGE_FEATURES += " package-management "' >> conf/local.conf echo 'CORE_IMAGE_EXTRA_INSTALL += " iperf3 phytool i2c-tools"' >> conf/local.conf echo "KBRANCH = \"socfpga_agilex5-ES_RC\"" >> conf/site.conf echo "UBOOT_BRANCH = \"socfpga_agilex5-ES_RC\"" >> conf/site.conf echo "ATF_BRANCH = \"socfpga_agilex5-ES_RC\"" >> conf/site.conf bitbake core-image-minimal
Make SD Card¶
Followed Intel's instructions but needed to make rootfs bigger because I used the full-cmdline rootfs so run the following instead at the end.
sudo python3 make_sdimage_p3.py -f -P fatfs/*,num=1,format=fat32,size=53M -P rootfs/*,num=2,format=ext3,size=512M -s 1024M -n sdcard.img
Booting the Board¶
- Make sure the USB cable is connected to J21 for the UART console, baud rate should be 115200
- Make sure the SD is in and the jumper J20 is on the 2 pins closest to the SOC
- Program the FPGA with mitysbc_a5e_hps.sof over JTAG
- When the board gets to the u-boot prompt enter the following to boot linux
fatload mmc 0:1 82000000 Image fatload mmc 0:1 86000000 socfpga_agilex5_socdk.dtb setenv bootargs console=ttyS0,115200 root=${mmcroot} rw rootwait; booti 0x82000000 - 0x86000000
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