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MF 02:46 PM FPGA Development: RE: Custom Loopback based on mSG-DMA Example Design

Max,
Glad to hear you have it working!
After giving this another thought, my guess may be that your FPGA design may still have been based off my previous FPGA design example. Then when I posted the new release, you may have just ta... Mike Fiorenza

MK 02:32 PM FPGA Development: RE: Custom Loopback based on mSG-DMA Example Design

Hello Mike,
Thanks a lot for your help.
I've implemented all the points you've mentioned.
This is very strange, I don't understand how this happened that SMMU was disabled and A5E Cache Coherency and DMA's had different setting than... Maxim Kanevsky

07/29/2026

DK 09:30 AM FPGA Development: RE: Custom Loopback based on mSG-DMA Example Design

> First things first: our example design is not a loopback.
> ...
It was understood after analyzing the example C code. But the first Visio picture is taken directly from documentation. Please update it.
Dmitry Kirilin

07/28/2026

MF 09:57 PM FPGA Development: RE: Custom Loopback based on mSG-DMA Example Design

Hi Maxim,
Thanks for the detailed write-up, and thanks especially for attaching the archive. I pulled your project apart and diffed it against our reference design, and I think I found your problem. Let me answer your example design q... Mike Fiorenza

MK 07:33 PM FPGA Development: Custom Loopback based on mSG-DMA Example Design

Dear Sir/Madam,
We are using your mSG-DMA Example Design and trying to make our custom Loopback based on this example design.
Please see attached to this message PDF file with drawings of Example Design and our Custom Loopback based ... Maxim Kanevsky

07/13/2026

EH 01:13 PM FPGA Development: RE: Not being able to Make jic

Good morning,
I have readded the PCIe RP IP, but it I still can't regenerate/update the a5e because the tool complaints about the hps emif.
Thank you,
Eleonora Eleonora Haralanova