Mity CPU Platforms » MitySOM-A5

08/21/2026

MF 05:15 PM FPGA Development: RE: PCIe Root Port bring-up on MitySOM-A5E (A5ED-B64-144-SRC-X) — hard system hang, likely missing GTS reset sequencer for right-side bank

Hi Brady,
Thanks for the details. Both of your fixes look correct and I think you're one step from the real problem (which you pointed out).
You moved the PCIe IP from the left shoreline bank to the right shoreline bank (the FMC), ... Mike Fiorenza

MF 03:23 PM FPGA Development: RE: Programming File Generation

Max,
Did you try clicking the Generate button? I think the GUI is just bugged stating that the SOF doesn't have the bootloader, however, your pfg file properly declares the bootloader path. Once I clicked generate it merged the SOF wi... Mike Fiorenza

08/20/2026

MK 07:33 PM FPGA Development: Programming File Generation

Hello Sir/Madam,
I'm trying to create Programming File Generator for our own project based on your example design. Your eaxample design uses Makefile that build, compile and generate programming Files. We have our own scripts to build... Maxim Kanevsky

BH 07:21 PM FPGA Development: PCIe Root Port bring-up on MitySOM-A5E (A5ED-B64-144-SRC-X) — hard system hang, likely missing GTS reset sequencer for right-side bank

Subject: PCIe Root Port bring-up on MitySOM-A5E (A5ED-B64-144-SRC-X) — hard system hang, likely missing GTS reset sequencer for right-side bank
Setup:
Board: MitySOM-A5E, part A5ED-B64-144-SRC-X, mitysom-a5e-ref-base project, pro_2... Brady Heater