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From 08/21/2026 to 09/19/2026
08/21/2026
- MF 05:15 PM FPGA Development: RE: PCIe Root Port bring-up on MitySOM-A5E (A5ED-B64-144-SRC-X) — hard system hang, likely missing GTS reset sequencer for right-side bank
- Hi Brady,
Thanks for the details. Both of your fixes look correct and I think you're one step from the real problem (which you pointed out).
You moved the PCIe IP from the left shoreline bank to the right shoreline bank (the FMC), ... - MF 03:23 PM FPGA Development: RE: Programming File Generation
- Max,
Did you try clicking the Generate button? I think the GUI is just bugged stating that the SOF doesn't have the bootloader, however, your pfg file properly declares the bootloader path. Once I clicked generate it merged the SOF wi...